Design And Test Of 8b/10b Encoder And Decoder Circuits Based On 2.5G SerDes

Nowadays, with the rapid development of information technology, in particular, development of high-speed transmission interface.Because of bottleneck on speed, the high-speed serial technology replace parallel transmission technology gradually, SerDes which used for high-speed Fibre-Channel become a mainstream interface technology gradually.SerDes is abbreviation of Serializer/Deserializer, SerDes is a mainstream TDM and P2 P high-speed serial interface technology, SerDes compose by reciver and sender. At the transmitting port, data is encoded by 8b/10 b encoder, serializer will convert parallel data which has been DC compensated to serial data, the LVDS transmitter will transmit the serial data finally. At the receiving end, LVDS reciver recive the serial data and convert it to paraell data by Deserializer, and 8b/10 b decoder revert the data.In this article, encoder and decoder are based on the patent of IBM Corporation. 8b/10 b encoding technology has a DC balance( in order to avoid data flow exists sequential 5 numbers “0” and “1”) characteristics, at the same time, control data flow by K codes(a special coding in 8b/10 b encoder). We design the RTL code by verilog HDL, we use logic and look-up table to realize the 8b/10 b encoder and decoder circuits, in addition, we count the logic resources and expand the circuits in this papper. Due to the importance of the encoder and decoder circuits in SerDes, we should simulate the circuits plenty. We simulate RTL circuit and analyze code coverage with modelsim, and simulate transistor-level with Hsipce. We ensure the correct function of the circuit by fully simulated.SerDes chip has complex strcucture, in order to facilitate the testing, the addition of the 8b/10 b encoder and decoder circuit in a BIST. Because of the Serdes chip is a hybrid digital-analog chips and digital circuits to achieve the main function. As a result in this article, we design a FPGA board to provid test stimulus and reference clock, test SerDes chip by FPGA board.