Research Of Power Mosfet With High-K Dielectric Trench

The proposing of super junction theory breaks the “silicon limit” of power MOSFET and establishs landmark of power devices. However, the issue of charge imbalance is always the key and difficulty of the super junction design and manufacture. In this paper, we studied the super junction SOI LDMOS and further proposed three new SOI HK LDMOSs with the combination of super junction theory and high-k dielectric, in order to optimize the trade-off of breakdown voltage and specific on-resistance.(1)We introduced the typical SOI Super Junction LDMOS. The adjacent P/N pillars in the drift region can deplete each other so the device can maintain the breakdown voltage while increase the doping of drift region. By simulation, we’ve got BV=179V and the specific on-resistance Ron,sp=5.3m?·cm2. Then we introduced the key fabrication process of the super junction structure.(2)An SOI LDMOS with trench filled of high-k material(SOI HK LDMOS)is introduced. This structure used the trench filled of high-k material to replace the P pillar adjacent to the N type drift region. The body region, high-k material and drift region formed an equivalent MIS capacitance structure. This equivalent capacitance assists in self-adapted depleting the drift region, reshapes the electric field distribution and alleviates the charge-imbalance brought by the substrate-assisted depletion effect. By simulation, we’ve got BV=212V and the specific on-resistance Ron,sp=4.6m?·cm2. Compared with the SOI Super Junction LDMOS, the specific on-resistance Ron,sp decreases by 13%~20%, the breakdown voltage BV increases by 16%~18% and the FOM(BV 2/Ron.sp) increases by 62%~68% based on different dielectric constant of high-k material. We proposed a feasible fabrication process which is simpler than the process of super junction structure.(3)An LDMOS with Semi-HK structure(Semi-HK LDMOS) is introduced. This structure used high-k material to assist in self-adapted depleting the drift region and reshape the electric field distribution in order to optimize the trade-off of breakdown voltage and specific on-resistance near to the source while the part of the drift region near the drain is lightly doped to further ease substrate-assisted depletion effect and weaken the sensitivity of the device to charge-imbalance. By simulation, we’ve got BV=169V and the specific on-resistance Ron,sp=4.8m?·cm2. Compared with the SOI Super Junction LDMOS, the specific on-resistance Ron,sp decreases 9%, the breakdown voltage BV decreases 5%, but it has greatly improved the issue of charge-imbalance. Finally a feasible fabrication process is proposed.(4)A high-k LDMOS with surface low on-resistance path(SLOP HK LDMOS) is proposed. This structure has a surface layer of heavy doped low on-resistance current path and so the device can reduce the specific on-resistance while maintain a high breakdown voltage with the lightly doped drift region. By simulation, we’ve got BV=213V and the specific on-resistance Ron,sp=4.3m?·cm2. The structure further reduces the on-resistance and only needs to add a mask and an ion implantation process.