Research On New Structure Of Trench Super Junction LDMOS Based On Charge Balance

With the development of Smart Power Integrated Circuit(SPIC),there are more and more requirements for power devices that can be integrated in SPIC,Lateral Double diffused Metal Oxide Semiconductor Field Effect Transistor(LDMOS)relies on its higher input impedance,integration level,switching speed,and lower power loss advantages,in SPIC has been widely used.However,due to the structural characteristics of semiconductor power devices,Specific on-Resistance(Ron.sp)and Breakdown Voltage(BV)are all restricted by their manufacturing materials,the length of the drift region,and the doping concentration of the drift region.The problem of "Silicon Limit"(Ron,sp ? BV2.5)also arises.In recent years,Super Junction(SJ)technology has been widely used in semiconductor power devices.The SJ technology has achieved a huge improvement in the voltage withstand capability of the voltage withstand layer by replacing the conventional single resistive voltage withstand layer with the junction withstand voltage layer.Its appearance broke the"Silicon Limit" of semiconductor power devices.The relationship between Ron,sp and?BV1.3 is realized.The development of integrated circuits is moving towards smaller sizes.However,because SJ LDMOS is also restricted by the length of the drift region,it cannot achieve an increase in breakdown voltage in a smaller size.Deep trench(DT)devices with the same cell size can increase the BV of the device by folding the drift region,extending the length of the drift region,and changing the material of the voltage withstand layer.Combine SJ technology with DT LDMOS can alleviate the problem that the breakdown voltage of the SJ LDMOS is limited by the length of the drift region.However,in the conventional DT SJ LDMOS,due to the formation of Silicon-Insulator-Silicon(SIS)parallel plate capacitors on both sides of the deep trench,the charge imbalance in the SJ region is generated and the performance of the device is reduced.Based on the theory of charge balance,this paper studies and analyzes the electric field distribution and charge of the SIS capacitor inside the device,and obtains a charge compensation method that returns the SJ region of the device to charge balance.By combining theory and TCAD simulation software verification,the structural optimization design and electrical characteristics simulation of the two new structures are carried out.(1)A Deep Trench Super Junction LDMOS with Triangular Charge Compensation Layer(TCCL DT SJ LDMOS)is proposed and optimized.The TCCL DT SJ LDMOS structure optimizes the electric field of the deep trench SJ LDMOS by introducing a triangular charge compensation layer in the SJ region on both sides of the deep trench,shielded the SIS capacitance effect,so that the SJ region as the drift region reaches the ideal charge balance state again.TCAD software simulation results show that,compared with the conventional DT SJ LDMOS,the BV of TCCL DT SJ LDMOS has increased from 498V to 730V,and the power figure of merit(FOM=BV2/Ron,sp)has increased by 12.8MW/cm2.Finally,the design of the key manufacturing process of the TCCL DT SJ LDMOS structure is carried out.(2)A Deep Trench Super Junction LDMOS with Double Charge Compensation Layer(DC DT SJ LDMOS)is proposed and optimized.DC DT SJ LDMOS adds a longitudinal variable doping charge compensation layer and a triangular charge compensation layer inside the conventional trench SJ device to shield the SIS capacitance effect and return the SJ region to a charge balance state.The design of the device structure increases the current conduction region in the on-state and reduces the specific on-resistance of the device.Compared with TCCL DT SJ LDMOS,the realization of process preparation is easier.Through TCAD software simulation,DC DT SJ LDMOS compared with the conventional DT SJ LDMOS structure under the same device size,the breakdown voltage has increased by 41.8%to 705.5V.The specific on-resistance of DC DT SJ LDMOS is 23.7m?·cm2,and the power figure of merit has reached 21.0MW/cm2.Finally,the design of the key manufacturing process of the DC DT SJ LDMOS structure also is carried out.