Modeling And Characterization Of Extended Gate Super Junction LDMOS Based On Charge Balance

With the development of semiconductor power devices,people have higher and higher requirements for the performance of power devices.In order to meet the increasing demand for quality,it is necessary to optimize the structure of the power device when designing it.Lateral Double Diffused Metal Oxide Semiconductor(LDMOS)is popular today because of its high breakdown voltage,low on-resistance and fast switching speed.In Metal-Oxide-Semiconductor Field-Effect Transistor(MOSFET),because of its breakdown voltage(VB)and specific on-resistance(RON,sp)The relationship is a positive correlation to the power of 2.5.High breakdown voltage and low specific conductance cannot be considered at the same time.But because of the emergence of Super Junction(SJ)devices,the relationship between the breakdown voltage and the specific on-resistance to the 1.3th power broke the traditional "silicon limit" of the 2.5th power of the device,and the application range of power devices is becoming more and more extensive.However,SJ LDMOS,which combines the advantages of the two,is affected by the substrate-assisted depletion effect(SAD).SJ LDMOS has a greater advantage in the lateral electric field,but its vertical substrate assists in depletion of SJ,which affects the charge balance of the super junction.In order to deal with the performance degradation caused by charge imbalance in the Super-Junction region,this paper proposes a new type of SJ LDMOS.By constructing its electric field,a model under the influence of the extended gate is given.Through the guidance of the model,the performance change of the new structure after the extension gate was added was explored,and this SJ LDMOS simulation was given for verification.And the specific design method is given for process manufacturing.(1)For the EG SJ LDMOS model,using the principle of electric field superposition,the transverse and longitudinal potentials in the device are split,and the charges generated by the super junction and EOS capacitor are calculated respectively,and the charges and electron speeds are integrated,and finally the specific conductance is obtained.The relationship between the on-resistance and the length of the drift zone.Reuse the obtained device model to optimize the device structure,so as to provide theoretical guidance for device design.(2)An EG SJ LDMOS(A ultra-low specific On Resistance and Extended Gate SJ LDMOS Structure,EG SJ LDMOS)is proposed and optimized.Different from the traditional surface SJ structure,the SJ layer of this structure is located in the main body of the drift region,and a layer of extended gate(EG)is added above the drift region.The extended gate,gate oxide layer and drift region form an EG Structure-Oxide-Semiconductor(EOS)structure.The drift region of this structure can obtain charge compensation and obtain an approximately rectangular electric field.In the off state,the linearly doped P-region can make the extended gate obtain a nearly rectangular electric field.At the same time,due to the electric field modulation of the EOS capacitor,the capacitor will cause the power line of the drift zone to turn and terminate at the P-zone of the EG structure.In the on state,the EOS structure can accumulate a high concentration of electrons in the drift region,which greatly reduces the specific on-resistance.The simulation results show that compared with the traditional SJ LDMOS,when the drift length is 24?m,the specific on-resistance is reduced by 84.7%,and the power figure of merit(FOM)is 18.9 MW·cm-2.(3)The process design method of EG SJ LDMOS is given,including epitaxy,photolithography and linear variable doping.In order to avoid the mutual influence between the LDMOS device and the linear variable doping of the EG region during Gaussian doping,a bonding process will be used in the EG region and the silicon wafer below.