New Structure Design And Experimental Research Of A 700 V LDMOS Based On FIN-SJ Conception

The high voltage integrated circuits are widely used in AC/DC converter,high voltage gate driver,LED lighting driver,etc.As the core switching device in the HVICs,the high breakdown voltage(V_B)and low specific-on resistance(R_on,sp)are required simultaneously in the LDMOS(Lateral Double diffused MOSFET).RESURF(Reduced Surface Field)is the most popular technology to improve the V_B-R_on,sp performance of LDMOS.Furthermore,the SJ(Super Junction)structure is generally used in LDMOS due to its superior V_B-R_on,sp performance while the SAD(Substrate Assisted Depletion)effect limit its V_B performance.Improving doping concentration for a decrease of R_on,sp and restraining SAD effect at the same time are the main development trendency of integrated SJ.This article realize a further performance improvement of integrated SJ by proposing a 700 V LDMOS based on FIN-SJ conception which combining the RESURF technology and SJ,the main contributions and innovation of this thesis are as follows:Firstly,the FIN-SJ conception and its mechanisms are proposed.The FIN-SJ refers to a fin-like arrangement of PN pillars,the N pillars are therefore depleted by three adjacent P pillars causes an increase of doping concentration.The PN pillars of FIN-SJ can be divided into two parts:the buried PN pillars which follow RESURF principle to introducing vertical PN junctions for the optimization of the surface electric field and restriction of the SAD effect;the surface PN pillars which is as same as conventional integrated SJ to introducing lateral PN junctions for a further optimization of surface electric field.In conclusion,the FIN-SJ realizes both lateral and vertical optimization of electric field causes increasment of doping concentration without the need for additional process.Secondly,the basic structure and process of FIN-SJ are optimized.The optimization of FIN-SJ was also divided into surface PN pillars and buried PN pillars,which are optimized according to the equivalent substrate model and design formula of integrated SJ,separately.Then,evaluating the current-carrying capability before and after the introduce of FIN-SJ with normalized current-carrying capability?_C,and an improved Y-direction and Z-direction unbalanced FIN-SJ structure was proposed accordingly.An optimized FIN-SJ structure,thermal budget and process is obtained through the TCAD simulations.Finally,a 700 V FIN-SJ LDMOS is experimentally verified.The layout design and experiments are based on a 700 V BCD process,a performance of V_B=763 V,R_on,sp=74m?·cm² is experimentally realized with a balanced FIN-SJ structure,which is 32.5%lower than the conventional Triple RESURF silicon limits.And a performance of V_B=796.5 V,R_on,sp=62 m?·cm² is realized by simulation,which is 49.3%lower than the conventional Triple RESURF silicon limits.