Study Of Trench SOI LDMOS With Super-junction Effect

Breakdown voltage?BV?and specific on-resistance(R_on,sp)are the most important electrical characteristics of silicon on insulator lateral double-diffused metal oxide semiconductor field effect transistor?SOI LDMOS?.While,for the restriction of contradictory relation between BV and R_on,sp of SOI LDMOS,it is hard to effectively improve their comprehensive performance by simply changing the length or the doping concentration of drift region.Some advanced techniques have been proposed to break through the restriction and improve the comprehensive performance of SOI LDMOS.Super-Junction?SJ?and Trench technique can not only significantly improve the BV but also markedly reduce the R_on,sp of SOI LDMOS,thus break through the contradictory relation between BV and R_on,sp.To reduce R_on,sp and improve BV of SOI LDMOS,a novel structure with heavily doping P/N pillars and vertical dual-trench-gates?P/N DTG-T LDMOS?and another novel structure with heavily doping L-shaped P/N pillars and vertical dual-trench-gates?LP/N DTG-T LDMOS?based on previous researches on trench SOI LDMOS?T LDMOS?are proposed.The P/N pillars form a SJ structure and cause assistant depletion effect in the drift region of the new devices.The two-dimension semiconductor device simulator TCAD MEDICI shows that the novel devices have lower R_on,sp and higher BV in comparison with the conventional T LDMOS.Besides,the gate charge characteristics,switching characteristics and temperature characteristics of the novel devices are investigated,the key process steps for fabricating the novel devices are also presented.P/N DTG-T LDMOS device enhances the withstanding of SOI layer and improves the doping concentration of drift region by introducing a P-type pillar and a N-type layer into the drift region under source.At off-state,the P-type pillar forms a revers PN junction with the N-type pillar and drift region,which introduces high potential into drift region from the interface and improves the electric field of drift region.Thus the BV of P/N DTG-T LDMOS is visibly improved.At on-state,the P-type pillar improves the doping concentration of drift region by causing assistant depletion effect on it,which significantly reduces the R_on,sp of P/N DTG-T LDMOS without cutting down the BV.In addition,the heavily doping N-type pillar further reduce the R_on,sp by forming a low resistance conducting path for the carriers.Finally,the BV of P/N DTG-T LDMOS is high to 192 V,improved by 13%in comparison with 170 V of the dual-trench-gates T LDMOS.The R_on,sp of P/N DTG-T LDMOS is low to 5.88 m?·cm²,reduced by 42%in comparison with 10.19 m?·cm² of the T LDMOS.LP/N DTG-T LDMOS device further enhances the withstanding of SOI later and improves the doping concentration of drift region by extending the P\N pillar along the bottom interface of oxide trench.At off-state,the L-shaped P pillar markedly improves the electric field in the bottom side and right side of the drift region,thus the BV of LP/N DTG-T LDMOS is improved.At on-state,the L-shaped P pillar improves the doping concentration of drift region by enhancing the assistant depletion effect.Thus the R_on,sp of P/N DTG-T LDMOS is further reduced.As a result,the of LP/N DTG-T LDMOS reaches a higher BV of 247 V and a lower R_on,sp of 3.61 m?·cm²,improved29%and reduced 39%respectively compared with the P/N DTG-T LDMOS.