Study And Design Of Low-power Analog-to-Digital Converter

In recent electric systems, the rapid advancement in wearable mobile devices, medical sensorsand micro-sensor networks has put forward higher requirements on the miniaturization of electronicsystems. In order to make these devices portable, it is necessary to design low-voltage, low-powerADC.First of all, several typical kinds of ADC architecture and their principle are presented andcompared. On the basis of0.13μm CMOS process, a10-bit,1MSps successive approximationregister analog-to-digital converter (SAR ADC) is presented. The DAC is implemented by usingsplit capacitors array with two separated5-bit arrays, which saves the area of capacitors array andreduces dynamic consumption by about37%. The boostrapped switchs for sample-and-hold areused for reducing the on-resistance of sampling switch and increasing sampling speed. During thecompactor design, three-stage pre-amplifier and two-stage dynamic latch cascode structure areadopted. Each pre-amplifier is optimized with input cascade MOS to impare the kickback noise.Diode-connected MOS transistors and reset switch are used as short-circuit plug to bridge theoutputs of every pre-amplifier respectively, and it accelerates the comparison. An improvedtwo-stage dynamic latch is applied at the end of latch stage，which further increases comparisonspeed and reduces the offset voltage. Simulation results show that the proposed comparator candistinguish0.1mV input at20MHz while its power is200uW. The successive approximation controllogic is designed by the method of full customization, which can achieve the smaller area and lowerpower compared with logic synthesis.The simulation results show that at a1.2-V supply, the sampling rate is high up to1MS/s with12.5KHz sinusoidal input. The simulated SNR and SFDR are54.47dB and45.18dB respectively.