Research On High-Speed Codec For Non-binary LDPC Codes

LDPC (Low-density Parity-check) code was proposed by Robert Gallager in1962as a kind of linear block code which have a sparse parity check matrix. The performance of LDPC can approach the Shannon limit, so LDPC is a hot sector in recent years. Davey and Mackay proposed Non-binary LDPC codes in Galois field GF(q) in1998. Such code words have better performance than the binary LDPC, and if the Galois field is larger, decoding performance will be better. In this thesis, a FPGA implementation of Non-binary LDPC codec is proposed, which steps further in LDPC theory and practice.First, in the Non-binary-LDPC encoder, based on the basic principles of the field operation, this thesis made a three-time-optimization hardware design, and specifically designed a corresponding module structure, which optimized the encoder operation process; this thesis also designed three kinds of encoder, including serial encoder based on FSM (Finite state machine), the parallel encoder based on pipeline structure, and partially parallel encoder. These three encoders have their own advantages, respectively suitable for different scenarios. These encoder was designed under the premise of saving on-chip resources, and maximizing the throughput.Secondly, considering the improved Non-binary-LDPC decode MS algorithm (Minimum sum)-IMS-2(Improved MS) algorithm can achieve a good tradeoff between complexity and performance, and easy to be implemented on FPGA platform, this thesis designed a decoder based on IMS-2algorithm. The check module of the IMS-2decoder uses a partially parallel structure; check node update module uses the address conversion instead of domain element operations, and uses the minimum difference rule to update the check node information; variable node update module uses the RAM array-simultaneously-process to update the variable node information. Multi-angle optimization algorithm effectively improves the throughput of the decoder.Finally, in order to verify the performance of the codec, this design implements all the modules on Xilinx Kintex-7FPGA platform, including encoding and decoding module, channel analog module. The thesis uses (90,45) Non-binary LDPC code in GF(16) as a code word to verify the simulation results. And results show that serial encoder, the parallel encoder, and partially parallel encoder can achieve the highest encoding rates of50Mbps,1.2Gbps, and600Mbps respectively, and the result is consistent with the software simulation results; the IMS-2decoder have265Mbps original information throughput, and132Mbps decoded information throughput, and can be achieved even higher.