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Design And Implementation Of Non-binary LDPC Encoder And Decoder Based On FPGA

Posted on:2015-10-10Degree:MasterType:Thesis
Country:ChinaCandidate:L H HeFull Text:PDF
GTID:2348330518972592Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
In the information age, a lot of information needs to be sent and spatial interference is serious, reliable communication becomes increasingly important. Channel coding has been a more imprtant role in the communication system. LDPC channel coding technology has been a hot research because of its high performance. In order to improve its performance,Research has ranged from the binary field to the nonbinary field. In this paper, nonbinary LDPC codes is researched, engineered solutions is proposed and achieved by FPGA.Firstly,research on schedule of study field of channel coding is followed up,and the study actualities of nonbinary LDPC code is described. Based on these, a reasonable hardware implementation is designed and researched.Secondly, the basic concepts of nonbinary LDPC codes is summarized. The form of a matrix from the parity check matrix structure is determined. The existing algorithm from different encryption algorithm is optimized to propose fast encoding of QC structure and mixed-domain decoding that suitable for hardware implementation.Again,this work takes use of Visual Studio software to build a communication system simulation model, and it uses this model to simulate and analyse multi-matrix construct,coding rate, code length, decoding iterations and the data quantization precision under Gaussian noise channel conditions .thus, hardware system parameters is achieved.Then, with the help of the Quartus ? software development platform, the hardware design for encoding and decoding algorithms of determined parameters the communication system is conducted. The encoder and decoder implementation is completed by Verilog HDL language and the timing analysis is conducted by Modelsim software, the hardware platform is determined, as well as the design and production after finishing hardware algorithm design.Finally, alone and in combination development the individual and associated system testing procedures are compiled by LabWindows software. The PC test interface is designed,and the functions of Codec are verified separately, then the joint system test for codec under Gaussian noise channel is conducted and the performance is compared with theory.
Keywords/Search Tags:Non-binary LDPC codes, Fast encoding of QC structure, Mix domain decoding, FPGA implementation
PDF Full Text Request
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