Design And FPGA Implementation Of Non-binary LDPC Decoder Based On EMS Algorithm

Low-Density Parity-Check (LDPC) codes have shown to have good error correcting performance that approaches the Shannon limit. Non-binary LDPC codes show significantly higher performances than binary LDPC codes. However, this improvement is achieved at the expense of increased decoding complexity. This thesis investigates some key problems of design and field programmable gate array (FPGA) implementation of non-binary LDPC decoder.The decoding algorithms for non-binary LDPC codes over finite fields GF(q) , such as the belief propagation (BP) algorithm, FFT-BP algorithm and extended min-sum (EMS) algorithm, are studied. The EMS algorithm is suboptimal, and naturally introduces a performance degradation compared with the BP algorithm. To reduce the decoding complexity, we have to focus on a local simplification of the check node processing.By theoretical analysis and simulation, the performances and computational complexity of EMS decoding algorithm are studied. The EMS decoding algorithm greatly reduces the computational complexity of processing units. The EMS algorithm is a good candidate of hardware implementation of non-binary LDPC decoders, since its complexity has been greatly reduced compared with that of other decoding algorithms for non-binary LDPC codes and the performance degradation is small or negligible.Based on principles of EMS decoding algorithm, the FPGA implementation method and structure are proposed, a 1044bits rate 1/2 non-binary LDPC code over GF(64) decoder is implemented on Xilinx FPGA Virtex-4 XC4VLX60, and all the modules in the FPGA design and the hardware simulation results are also introduced.