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Research And Design Of High-precision High-speed ADC For Image Sensors

Posted on:2016-06-26Degree:MasterType:Thesis
Country:ChinaCandidate:Y Y GuoFull Text:PDF
GTID:2308330467498737Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Image sensor is a device that converts an optical image to electronic signals. It isa mixed integrated circuit contains the pixel array, analog circuits and digital circuits.According to the latest market research report, from2014to2020, the image sensorsmarket will be growing at an average of10.6%, and it is expected to reach$16billion in2020. In this big market, the image sensor is required by many fields, suchas scientific research, crash tests, high speed scanning, machine vision, militarystudies and so on.Generally speakingļ¼Œthe ramp ADC is still dominant in the analog to digitalconverters for applications of image sensors. However, due to limitations of its ownstructure, ramp ADC will become the bottleneck of the design of high speed COMSimage sensors. Among the many other types of analog-to-digital converts, successiveapproximation analog-to-digital converter has the advantages of high accuracy, highspeed, low power consumption and small chip area. The advantages mentionedabove are what the image sensors needed. So SAR ADC is the first choice of highspeed CMOS image sensors design.This thesis presents the design of a10-bit20MS/s differential SAR ADC forhigh speed CMOS image sensors. It mainly consists of the sample-and-hold circuit,comparator, asynchronous clock generation circuit, SAR logic control block andDAC. By optimizing the architecture, the proposed SAR ADC has the halfcapacitors and the18.74%average switching energy consumption compared withconventional SAR ADC.The proposed SAR ADC is fabricated in0.18um CMOS technology andoccupies an area of750x135um2. This SAR ADC consumes about750uW energy at1.8V supply. After completing the layout design of the SAR ADC, the SAR ADCachieves an ENOB of9.89bit, an SNDR of61.33dB, an SFDR of77.09dB with a 566.4kHz sinusoidal input at20MS/s sampling frequency. And the reliability of theabove result is verified by corner simulation. After the tapeout, the SAR ADCachieves an ENOB of8.63bit, an SNDR of53.76dB, an SFDR of67.31dB with a112kHz sinusoidal input at20MS/s sampling frequency.
Keywords/Search Tags:Image sensor, successive approximation analog-to-digital converter, capacitance DAC, bootstrap switch, asynchronous clock generation circuit
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