Design And Implement Of H.264Baseline Profile Decoder

With the development of communications, electronics and computer technologies, human society has entered a multimedia age. Obviously, H.264video coding standard has an important position in this age. The high-speed, low-power H.264codec chips are undoubtedly one of the most important parts.A video decoder of H.264baseline profile is designed with SMIC180nm1P6M standard CMOS technology. The main contents of this paper include:1. The basic theory of video compression and H.264video codec protocol are studied, and then the key technologies of H.264are studied and analyzed deeply.2. Based on the features of the key technologies, the pipeline and parallel structures of the entire decoder are proposed. Then the sub-modules of the decoder are proposed, the respective pipeline and parallel structures are used inside each sub-module. Finally, the verification plan is proposed, and the functional simulation for the entire decoder is took place. The result shows that the decoder can decode H.264video bit streams correctly.3. Using SMIC180nm1P6M standard CMOS technology, the RTL Verilog HDL code is synthesized and placed&routed. And then the RC parameters is extracted, the propagation delay is calculated and the post-layout simulation is took place. The result shows that the decoder can decode H.264video bit streams correctly.The decoder can decode H.264baseline profile of1920×1080-resolution at24fps with a clock of100MHz. It dissipates151.6mW at1.98V. The chip contains159K gates and20096bytes on-chip SRAM with1670.24um×1662.88um.