VLSI Design And Implementation Of High Performance CABAC Decoder

Context-based Adaptive Binary Arithmetic Coding (CABAC) is one of the H.264/AVC entropy coding styles. Compared to other entropy coding styles such as the ontext-based Adaptive Variable Length Coding (CAVLC), CABAC has higher coding efficiency. It has more than 10% to 15% compression efficiency improvement under the same picture quality. But the CABAC has more complex hardware architecher because of its algorithm complexity. If we use software to make real-time decoding, the CPU operating frequency must be need to archieve the Gs degree, so hardware design is used to speed up the decoding. However, congsidering the high CABAC algorithm complexity and the high degree of dependence, to implement an efficient CABAC decoder in hardware shoule be need to overcome many challenges.This paper focused on CABAC decoder prototype chip design and implementation. The major tasks of this paper are as follows:(1) CABAC decoder circuit area has been optimized. A new context index generator circuits have been proposed, non-residual part of the context incremental was set to a single table, while the majority of the context offset indexes were generated by the logic circuit. The area of the context index look-up table are reduced to 768bits, greatly reduced the look-up table area.(2) CABAC decoding rate has been optimized. By using the redundant circuits and parallel circuits, context index generator module and the context model memory were splited into two parts. As the same time, the probability memory has been duplicated. So part of the decoding process for syntax elements can achieve pipeline operations, which can reduce the probability of pipeline suspension to improve the decoding speed. Bypass decoding has been used to accelerate the decoding. The decoder can decode 2 bypass bits or one regular bit and one bypass bit per cycle when necessary. A simple First One Detection Logic circuit has been used to enable the process can be completed in one cycle. A single barrel shift register has been used to achieve the function that variable-length code stream can be read continuously. Simulation results show that CABAC decoding speed achieves 1.75cycle/bit. This decoder was compared with a normal CABAC decoder (A single generation circuit of context index is used, no pipeline) in decoding performance and area. The result showed that the mentioned framework has 2 times decoding speed improving under the 9.3% area increment compare to the normal decoder. (3) CABAC decoder has been designed and implemented. The proposed hardware framework was implemented with Verilog language, simulated with EDA software, varicated in the FPGA, synthesized with EDA synthesis tool. The decoder has been integrated into the H.264 decoder, and implemented on FPGA prototype. The maximum frequency of the decoder is 100MHz. The average decoding rate is 1.75 Cycle / Bin, which has met HD1080i format video real-time decoding requirement. The decoder implemented in a 0.25-um silicon technology, the area is 1,616,667.5 um2 ,and the maximum frequency is 166.7MHz. The dynamic power consumption is 23.8987 mW ,and the static power consumption is 738.5497 nW ,when the clock frequency is 100MHz.