Optimization Algorithm And VLSI Design Of RS Decoder Based On DVD Application

RS (Reed-Solomon) code has been widely employed in data transmission and storage systems owing to its excellent capability for correcting burst errors and random errors. Based on the research of RS code theory, analysis of DVD specification, and optimization improved from algorithm, this paper presents a full-process pipelined Errors-and-Erasures correcting Reed-Solomon Product-Code (RS-PC) decoders chip for DVD application. It features full-process pipelined, high-speed decoding, high performance correcting, simpleness of control timing, succinctness of circuit implementation, area efficient, and with good extend capacity. It can correct errors-and-erasures introduced in the process of storage and recovery of DVD data and also can be used as an IP core in the design of DVD servo chip.The main module of the RS-PC decoder chip are two pipelined Errors-and-Erasures correcting RS decoders and a block buffer manager. The RS decoder features an area-efficient key equation solver using a modified Euclid algorithm, which reduced the complexity of the design. Based on the methods of modules reuse, the proposed RS decoder are very regular and area efficient. Using three stage pipelines, the RS decoder can operate at a rate of 1 byte/clk. Based on a method of 2 dimension data rearrange, a high speed and high efficiency implementation of DRAM access is proposed in the design of block buffer manager. Using the block buffer manager with off-chip DRAM, a (182,172) row RS decoder and a (208,182) column RS decoder can be pipelined, which double the speed of RS-PC decoder and get a rate of 1 byte/clk.Based on the DVD specifications, the RS-PC decoder chip design is defined. The Matlab model of RS-PC encoders and decoder is presented for the verification of the algorithm. The hardware of RS-PC decoder chip is described in the Verilog HDL, function simulation and timing verification are processed, and then is implemented in a Altera FPGA. Through the function simulation and timing verification, the proposed RS-PC decoder meet the expected performance requirement, which gets the rates of one byte per clock, gets the max row error correcting of 5 errors of 10 erasures and the max column error correcting of 8 errors or 16 erasures, gets a data rate 40Mbytes/s interfaced with 100MHz SDR DRAM, which meet the 12×DVD performance requirement.