VLSI architectures for LDPC encoder/decoder in WiMAX

One of the main goals of any communication system is to transfer data reliably from source to destination. In particular, wireless communication medium is very noisy, so new techniques are to be used for error-control to ensure robust data transmission. Channel coding is the most popular and widely used error-control technique that makes use of channel codes. Shannon, considered the father of modern information theory, showed that every channel has certain threshold data-rate called the capacity below which reliable transmission is possible and above which transmission will result in un-recoverable errors. Thus, the goal of every channel code is to come as close to this limit as possible and still be practical to implement.; Turbo codes introduced in 1993 and Low-Density Parity-Check (LDPC) codes first introduced in 1963 are among such powerful channel codes. These LDPC codes were forgotten for 30 years because of their implementation complexity and lack of advancements in VLSI technology, until their rediscovery in the early 90's. Fortunately, recent advancements in VLSI technology have made it possible to implement LDPC decoding algorithms. Additionally, LDPC decoding algorithms can be highly parallelized and implemented more efficiently. Because of the above key advantages, LDPC has been adopted in all the emerging wireless standards. With the advent of these new wireless standards, the envelope of data rate is being pushed even higher. These requirements translate into high speed implementation of various channel coding schemes and at the same time these designs should occupy lower area and power.; The serial architectures for LDPC encoder/decoder available in literature are not capable of achieving high throughputs and other parallel structures do not provide a generic and a scalable architecture to support multiple standards. This Master's thesis implements a high throughput VLSI architecture for LDPC encoder as well as decoder. The proposed structure is also generic and scalable, supporting multiple standards. A generic scalable min unit is presented, which performs min-sum decoding, an approximation of the original belief propagation algorithm used in the decoding of LDPC codes. The proposed LDPC decoder is implemented as a parallel structure with high degree of pipelining. It supports any regular/irregular LDPC codes from any standard that define parity check matrix as a combination of identity matrix, shifted identity matrix and all-zero matrix. This architecture was synthesized using standard TSMC 0.18mum process technology with supply voltage of 1.8V. The achieved gate count of the proposed LDPC encoder and decoder was 71K and 810K (with full pipelined datapath), respectively.