Research On Techniques Of VLSI RT-Level Automatic Functional Vectors Generation

Functional verification is one of the most important techniques used to assure the correctness of VLSI design. Due to the increasing design complexity, functional verification is now the major bottleneck of the entire design process. Currently, functional verification concentrates on RT-Level or even higher levels to assure the RT-Level or high-level descriptions conform to the design specifications.Two primary approaches, simulation and formal verification are often used for functional verification. Formal verification techniques can prove whether designs are conformed to the design specification by static analysis techniques without test vectors. While simulation-based approaches verify designs by dynamic running with large amount of test vectors. However, both techniques encounter some difficulties in dealing with the increasing circuit complexity. The major problem of the simulation-based approaches is the lack of metric to gauge the quality of the verification, and needs large amount of test vectors to stimulate various corner cases of the design. Formal verification techniques are often limited by the computation resources when dealing with large circuits.Therefore, the coverage-driven approach, which combines the ideas of simulation and formal verification, is proposed and rapidly, getting popular. Some well-defined functional coverage metrics are used in this approach to perform a quantitative analysis of simulation completeness. With the coverage reports, the verification engineers can focus their efforts on the un-verified areas and generate more test vectors by the help of formal techniques to achieve better functional coverage. Among the techniques used in coverage-driven verification framework, the automatic functional vectors generation technique is the most important one. The vectors generation engine takes the coverage metrics as the goal for vectors generation, while relies on the coverage analysis techniques for further generation.The progress of the studies on automatic functional vectors generation is introduced in this thesis. The existing approaches are classified into several categories. The representative methods in each category are introduced and the advantage and disadvantage of each category are analyzed.In order to deal with large designs, one possible solution is to use abstraction techniques. A novel design abstraction and extraction approach based on program slicing technique is proposed in this thesis. We alter the slicing criterion of the traditional slicing method, so the related design for the given signals can be extracted without indicating line number. We also improve theslicing formula, which makes our method become more precise for extracting designs between two sets of signals. A new structure - process dependence graph and the slicing algorithm based on it are proposed, which can slice on concurrent programs. At last, an elegant theoretical basis based on program slicing for circuit extraction from Verilog description is developed.The existing VCD (Value Change Dump) file based coverage analysis method is improved in this thesis by only replaying the simulation of the control statements in the HDL description. We can gain speed up in coverage analysis with more than 2 times than existing method.This thesis defines novel state-pair coverage metric. By proposing the state-pair space traversal algorithm for interacting FSMs based on P-ROBDD, an algorithm that generates functional vectors for state-pair metric is proposed. The experimental results show that this algorithm is efficient in memory usage with several times of magnitude in memory usage reduction and perfectly solves the states space exploration problem.A novel method for automatic generation functional vectors from HDL descriptions based on path coverage and constraint-solving techniques is presented in this thesis. It only generates constraints for condition expression of the control statements in the given path, and bases on DD model derived from HDL description to propagate the intermediate values to the primary i...