High Speed Data Transmission Technology Based On PCIe

With the rapid development of information technology,the requirement of the quality of information to the people increase.Increasing the resolution of the audio, image and video information, making information data volume has increased dramatically.Once a digital movie`s size ranges from 700 MB to 1.5 GB, but now a 90 minutes of high-definition movie`s size reaches 30 GB.A high demands are put forward by today`s development situation on data transmission and storage capacity.The hard disk capacity in computer increases from gigabytes to terabytes,and the medium of hard disk is transition from mechanical hard disk to the SSD.Under the request of the high rate of computer system,interactions between a processor with a external device through the PCIe interface has become to the main way in computer architecture. In the current processor system, all peripheral devices access system directly or indirectly through the PCIe interface.In this paper,the main research content is based on the PCIe bus interface of high speed data transmission technology.A hardware scheme on high speed data transmission is put forward through the study of the PCIe interface.This technology solves the bottleneck of data transmission and improves greatly the data transmission rate between computers. This paper mainly studied the following content:1.PCIe data transmission card’s hardware design based on PCIe bus interface, data transmission scheme design, and internal system module division.In sending board using DMA transmission mode based on PCIe bus interface reads the data in the system memory, and save them in the DDR3 SDRAM large-capacity cache, at last,sends the data to receiving card by coaxial cables.In receiving card,the received data are buffered in DDR3 SDRAM and then sent to system memory using DMA based on PCIe bus interface.2.Design a large-capacity cache using DDR3 SDRAM.Use DDR3 SDRAM as a virtual FIFO to implement buffering data.DDR3 controll state machine and upstream/downstream FIFO solve the problem about the clock domain crossing and the data width change.The capacity of this virtual FIFO is 1 GB and the frequency it works is 250 MHz.In order to interface with PCIe IP core, the data width is 64.3.Design a DMA controller which based on PCIe bus interface.This controller contains a DMA controll state register file to store the DMA parameter such as DMA address and DMA block size.Sending engine and receiving engine implement receiving and sending transaction layer packages.According to the request of protocol,this paper studies both the management of Tag label in transaction layer packages and the handle of theout-of-order packages in reading completion packages.At last,design the state machine in both sending engine and receiving engine.The implement of the PCIe protocol in the design is mainly provided by Xilinx company’s IP core.Transaction layer is the only one need to be carry out.In addition,DDR3 controller is also provided by IP core.In this paper,the author designed a DDR3 controll state machine to be a interface between the DDR3 controller and the upstream/downstream FIFO.Using IP cores in designs have been the most popular design method.This method have greatly reduced the development cycle and the development cost. At the end of this paper,the author tests the design card.According to the test results,the transmission performance of this high speed data transmission system based on PCIe bus are obtained,and according to the test results, the reasons of the data rate are analyzed in theory.At last,the development trend and the theoretical data rate in future are discussed.