Design And Implementation Of The High-speed Large-capacity Solid-state Storrage System

With the development of science and technology, equipment signal environment is more and more complex, and more and more short development cycle. In the system development and testing phase, an electromagnetic signal in real time and high precision in the testing process to record the mass storage system becomes necessary. Through the recorded data storage system, can be improved algorithm is analyzed, the research or design. To meet the needs of test, this kind of storage system must have a high bandwidth and large capacity.Under the background of the project requirements, this paper analyzes various indicators, and overall design of the system is given. With SSD solid-state disk to store the carrier, through the use of parallel SSD disk reading and writing way, achieve the goal of high bandwidth transmission, large capacity storage; For Xilinx company Virtex- 5 series FPGA development platform, realize the SATA interface of solid-state disk storage controller, and through the instantiated multiple SATA controller to implement the form of RAID0 disk array; Use Rocket IO high-speed transceiver in the FPGA hardcore to implement high-speed serial data transmission, on the one hand, complete system and the acquisition module of external interface, on the other hand to complete the system and data communication between the solid plate; The DDR2 SDRAM memory as the cache system, solve the problem of data transmission speed does not match. Paper main work is as follows:1. Analyzed Rocket IO high-speed transceiver structure, properties, and functions of the main modules and the way to work. Design to realize high speed data transmission function, and complete the Virtex- 5 Virtex FPGA with data acquisition side Virtex- 6 FPGA communication test.2. Based on SATA2.0 protocol, designed by the application layer, transport layer, link layer and physical layer of SATA controller architecture. Based on the physical Rocket IO high-speed serial transceiver based on communication, using VHDL hardware description language to realize the OOB signal module and status control module, and through the OOB signals and solid-state disk to establish communicationlinks; Designed and implemented in the link layer module, CRC check scrambler send and receive module and control module, send and receive the frame of the CRC check, scrambling and solution are the one, and through the primitive interactive control function; Design of the transport layer frame encapsulation, frame parsing and status control module, data and command frame assembly and frame of analytic functions; Analyzed the embedded PLB bus, by giving the SATA controller configuration PLB bus interface, making it the user in embedded system based on FPGA IP core, the flexibility is invoked; Embedded processors are introduced Power PC, through advanced language implementation command sent by the application layer.3. By MIG tool for the design of DDR2 SDRAM memory cache was tested, verified the validity of the design. Finally used in the storage system of MPMC to control the DDR2 SDRAM. Tested external interface module design, the multiplex Rocket IO transceiver receive data caching data acquisition end, complete data splicing, a conversion function such as wide,finally, by NPI interface for access to the MPMC.4. Finally, on the SATA controller, NPI controller, the cache module each module function on the basis of a single test, using EDK tools based embedded storage system based on FPGA, tested on disk array composed of multiple SSD disk read/write control performance, the test results show that the designed by this paper is based on high speed serial transmission of large capacity solid state storage system work is stable, good performance, satisfies the requirement of system requirements of the proposed indicators.