Research And Design Of Logic Synthesis Methods Based On FPGA

Logic synthesis as a key optimization step in FPGA supporting software, its optimization result affects the performance of the following operations directly, such as placement and routing. Aiming at it, this thesis researches on the logic synthesis from two phases: technology independent and technology dependent logic synthesis. In technology independent logic synthesis, a don't care set optimization method based on maximal sets of permissible functions is introduced and implemented in the thesis. A comparison is conducted among network restructuring, two-level logic optimization and the approach implemented in the thesis. In technology dependent logic synthesis, a rewiring algorithm based on set of pairs of functions to be distinguished for post-mapping LUT is proposed. In the algorithm, the definition of similarity degree, the approach of building bipartite graph, and the area-oriented and delay-oriented heuristic methods are proposed and compared with the existing rewiring algorithms. The results illustrate that the method based on MSPF can achieve better optimization results and local optimal results or near-optimal results can be obtained by some combination of network restructuring and node minimization operations; the rewiring algorithm proposed in this thesis has higher rewiring and LUT optimization ability in the same time complexity with other rewiring algorithms.