| VLSI design is a complex process. It includes design specification, validation, verification, high-level synthesis, logic synthesis, physical layout, and chip fabrication. Each sub-process requires sophisticated computation and debugging; thus it represents a significant investment. In order to meet the time-to-market and budget constraints, it is desirable that such investments can be reused during the current development or in the next production cycle. We classify these practices into two categories: hardware-reuse and design-reuse.; Efficient reuse provides a fast time-to-market, preservation of design investment or even the reduction of the total design costs. In this thesis, we study three reuse issues arising in VLSI design processes, including field programmable gate array (FPGA) architecture designs, logic synthesis algorithms for engineering changes, and low-cost scan design methodology.; Field programmable gate array technology offers tremendous opportunities for rapid-prototyping, low-volume production, hardware emulation and customization of computing machines. The major feature of an FPGA is user-programmability. Using off-the-shelf user-programmable FPGA parts, a new system can be designed and verified in a few days. However, due to the pre-fabrication of the re-configurable resources, the utilization of programmable logic cells is usually low. The low utilization becomes more apparent when designs become larger. In this thesis, we analyze this issue and develop new methods for designing cost-effective programmable logic cells and routing resources.; In a typical VLSI design process, specifications were often changed in order to correct design errors and accommodate changes. Since a large engineering effort may already have been invested, it is desirable that these changes in specification will not lead to a very different design. This is called the engineering change (EC) problem. As automatic logic synthesis becomes popular, the issue of how to handle engineering changes gains even more importance. This is because synthesis tools usually perform global transformations to achieve good quality results. Small and local changes in the specification could have global effects and produce a very different network. In this thesis, we develop a logic synthesis algorithm for handling the engineering change problem at the logic level. Given a new specification and an existing synthesized logic network, the algorithm reuses the existing network such that the new specification can be realized with minimal changes.; In addition to designing correct functionality of a circuit, it is important to test it after fabrication. Sequential circuits have low testability due to the lack of controllability and observability of the flip-flops. To enhance testability, design-for-testability (DFT) methods such as full scan and partial scan have been proposed. Both scan techniques connect the selected flip-flops into a shift register to directly control and observe the flip-flops. However, the area and delay overheads imposed can be significant. To alleviate the above DFT penalty, we develop two low-overhead scan design methods, which exploit the controllability of primary inputs and a new test point insertion technique, to establish scan paths through the existing functional logic. Consequently, we can reuse the functional logic, for testing purposes and reduce the area and delay overhead. |
