A 2-5 Gbps fully differential 3X oversampling CDR for high-speed serial data link

This thesis reports a fully differential 3X oversampling dock and data recovery (CDR) circuit for burst-mode high-speed serial data link. The CDR operates at a multiple data rate from 2 to 5 Gbps. The architecture of the CDR replaces the analog VCO and loop filter, used in an analog PLL based CDR, with digital circuits. The CDR uses a digital threshold decision technique to improve the jitter tolerance performance.;The complete design flow is executed for the CDR circuit in 65 nm CMOS process technology. The whole CDR is designed based on current mode logic (CML) circuits. The functionality of the CDR is verified by post-layout simulation with pseudo random bit sequence (PRBS) of 27---1. The waveforms of incoming data, recovered data and dock are presented. The power consumption and chip area also obtained from post-layout simulation. The CDR consumes 39 mW of power from 1.1 V supply at 5 Gbps. The core CDR circuit occupies an area of 0.013 mm2. The performance parameters of the CDR are compared with recently reported digital CDRs.;First the system level CDR analysis is reported, which includes the CDR architecture and operating principle, and derivation of jitter tolerance and acquisition time. It is critical to know the amount of jitter that can be tolerated by the CDR in order to recover the data with satisfied bit error ratio (BER) performance. The jitter tolerance of the CDR is estimated by an event-driven simulation model developed in Matlab. The simulated results show a very close match to the theoretical values. The CDR has a high frequency jitter tolerance of 0.67 UI and an acquisition time of 8 Baud periods.