Font Size: a A A

Backend Implementation Of HS32K Chip Engineering Group Tape Out

Posted on:2016-01-05Degree:MasterType:Thesis
Country:ChinaCandidate:Y W ShanFull Text:PDF
GTID:2308330464458904Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Nowdays, as the rapid development of IC, Chip(SOC) gradually become the focus of the industry.SOC design process is mainly from the front design to the backend implementation, usually needed a long design cycle. Front design mainly includes the RTL code compile; gate-level netlist synthesis; static timing analysis.The backend implementation mainly includes the overall place-and-route; power consumption analysis; physical test and verify.Now technology has entered the stage of VDSM. the problem such as time delay、signal integrity、antenna effect has been increasingly serious,which restricts the development of today’s IC. To resolve the three questionshis, the paper carries on the thorough research and puts forward the solution that applied to the physical design of HS32 K chip.HS32K chip adopts HJTC 110 nm technology with working voltage 1.5V,working current 30 m A. We use the tool of Design Compiler、IC Compiler、Prime Time to analyze problems,such as timing、power consumption、congestion degree.Based on the physical design of the HS32 K chip, this thesis introduces the whole process of the chip backend implementation. we detailedly analyse the key steps of the establishment of physical environment、layout planning、IO and standard cell layout、clock tree synthesis、wiring design. Based on the traditional method, we analyse and verify the each steps of timing. After the clock tree synthesis, using useful_skew to repair setup time violation. When getting the GDSII file and netlist file, we carry on timing、the expected function test; check the problem of DRC、LVS and complete restoration of antenna effect. Finally, we achieve the engineering group tape-out of HS32 K chip.The thesis’ s main opinions are as follows:After the clock tree synthesis,boldly using useful_skew to repair setup time violation, achieved excellent effect.When the routing completed, there are still two shorting problems. Removing a little power grid nearby to increase routing channel. Using IC Compiler tools to wrap automatically, succeeding repaired the two shorting problem.
Keywords/Search Tags:SOC chip, place-and-route, VDSM, useful_skew
PDF Full Text Request
Related items