Design Of PCI Target Secure Chip

From the emergence of PCI (Peripheral Component Interconnect) in 1993, PCI has been widely adopted as a high performance bus protocol and used in various systems ranging from portable computer to supercomputer. The thesis discusses how to design a chip, which works as a target PCI device, and provides its semi-custom design method based on standard-cell library. The chip will facilitate the communication between devices on the add-in card and PCI local bus. The OTP ROM integrated in the chip will provide user an easy way to store secureinformation which should be protected.In accordance with design methods adopted in VLSI design, which deal with a design from highest abstraction to the lowest, the thesis discusses the design method of PCI target secure chip in three different abstraction levels listed below: i. System level design. In this level, the thesis provides the systempartition method, function design and method of design based on finite state machine. The key is the modification of available soft IP and realization of AD bus reuse technology.ii. Behavior level design. Taking PCI-MicroWire?interface module as an example, the thesis details the design method of modules in the chip at behavior level.iii. Physical level design. After a brief description of ASIC design flow adopted by PCI target secure chip, the thesis make great emphasis on various methods and skills used in physical design and verification with Apollo II from Synopsys.Several simulations have been made to guarantee the ideas' validity in the thesis and waveforms have been provided. During the discussion of each step in physical design, many optimization methods have been provided with theories' supporting.At the same time, the method of integrating hard OTP IP from third party has been deeply described from each stage in ASIC design flow.The chip discussed in this thesis has been taped out successfully in CHARTERED 0.35um technology and passed the verification.