The Udsm Soc Chip Layout To Achieve

SOC design technology comes into being under the trend of transition from IC to IS(integrate system), and now it has been becoming the mainstream of IC design. There are three distinct characteristics in SOC design:1. Integrates various IP cores; generally includes MPU, MCU, Analog IP core, Digital IP core, Interface circuit, and Ram or Rom etc.2. Large in scale, usually exceed one million gates, even to 10 million gates.3. Adopts VDSM Process technology However two outstanding problems are faced to IC layout design when the feature size reaches to 0.18μm or lower:1.Timing convergence problem seriously affects the circuits schedule ,and the interconnect-delay has exceeded more than 70% of the total circuits'delay.2.SI problem, usually it consists two aspects of IR-drop and Crosstalk. These problems often affect the chip function after tapout.Facing all the challenges of the VDSM design, this thesis presents one kind of place-and-route strategy based on continuous convergence. With the technology one wonderful floorplan with good placement and high routebility can easily be achieved. And then a design method to estimate the routebility in the beginning of the physical design of a chip is put forward.Finally, all the methods are used in an actual project, which show their efficiency. The goal of the project is to design one SOC chip for DSP, which contains over 7.5 million gates. With all the methods above, a wonderful floorplan with good placement and high routebility and low power and timing convergence has been achieved. According to the schedule ,it can be taped out next July.