White LED Driver Chip Circuit Layout Design And Verification

With the continuous improvement of chip integration and scale,the verificationworks is also on the rise at all levels of the design.Chip processing technology continuesto progress a higher challenge to the physical verification,more advanced technology,thesmaller the line width,the greater the resistance connection,and connection spacingdecreases increase the parasitic capacitance between the lines,Through-holeresistors,capacitors,the parasitic capacitance of the floating node will affect theperformance of the circuit,Parasitic parameters can be accurately extract becomingincreasingly important,more stringent requirements for EDA tools. For verificationtools,how to verify the data file of the entire chip is a problem that must be solved,Thismakes the DRC(design rule checking),LVS (layout Versus schematic) and PEX(parasitic extraction) is becoming increasingly complex and important.It has a vital roleto eliminate errors, reduce the design cost, and reduce the risk of design failure.Thevalidation process is a feedback mechanism to help design engineers to verify theterritory,to ascertain the problems and deficiencies, The ability to easily debug orcorrection problem, capacity and run time of the tool is the key to these tools.Layoutphysical verification provided by the Mentor Graphics Calibre is a good solution tothese problems,A good inspection capacity and performance, flexible and efficient use,the results browser glance, so that it gradually became deep submicron physicalverification industry standards, Currently, Calibre has been many design companies, celllibraries and IP developers and foundries standard framework for the handover.This paper combines the engineering design examples，design a6-channel LEDdriver chips in CSMC the0.5um DPTM technology for physical implementation. First,the layout placement and routing,Determining the location of the various functionalmodules and inter-module connection relationship,so that the signals between themodules can be reasonable flow. Good for wiring planning their position. Then use theCalibre verification tools to complete the entire territory of the back-endverification.After completion of the DRC and LVS verification, using Calibre PEXparasitic extraction tool to extract the device connection parasitic resistance and capacitance parameters to generate Hspice parasitic parameter circuit netlist simulationand chip tapeout functional test for each module.