The Research And Design Of Nano-scale SRAM In Low Supply Voltage

With the feature size falling into nano-scale, the integration of chipand the operation speed of the transistor have been improved significantly.However, power consumption will increase. Due to the use of mobilephones and other mobile devices, the demand for lowing power isincreasing. Reducing the supply voltage is an effective way to decreasingpower consumption. However, with the supply voltage reduced, theperformance of SRAM will be influenced. Therefore, the research ofSRAM in low supply voltage is very important.The main target of this paper is to improve the performance of SRAMin low supply voltage. After studying about SRAM structure, we analyzethe impact on SRAM by the method of lowing voltage. Then, some kindsof read and write assist circuits have been introduced, and compared theiradvantage and disadvantage. The improvement by negative bit line isobvious, and its side effect is small. So, the negative bit-line voltage(NBLV) scheme becomes the main object of this paper. ConventionalNBLV scheme generates negative voltage by using capacitor couplingprinciples. The absolute value of the negative voltage will increase withsupply voltage rising, This will cause some problem, such as writing theerror data into the bit cell mistakenly, and degrading the gate oxidereliability of the pass-gate device, etc. In this paper, a pre-discharge negativebit-line voltage (PDNBLV) scheme is presented to solve the problemsarising from conventional NBLV. By reducing voltage difference betweenthe two ports of the capacitor which is used to generate negative voltage athigh supply voltage, the absolute value of negative voltage generated by PDNBLV is lower than conventional NBLV, while there is no effect at lowsupply voltage. Furthermore, we propose tracking bit-line voltage circuit tocontrol the timing of generating negative voltage accurately, and sharedcircuit approach to save the area and power consumption.The proposed PDNBLV scheme is implemented in TSMC40nmCMOS technology. The result shows that the scheme improves the writeability in low supply voltage. The lowest operation voltage can be drop to0.6V. And PDNBLV makes the negative voltage suppressed in a reasonablerange, which can significantly extend the using life of transistors andimprove the product yields. At high supply voltage, it saves nearly20%power consumption only at the expense of3.26%area overhead.