VLSI Design For Discrete Cosine Transform

Discrete cosine transform (DCT) is the core of most international image compressing standards. Owing to its heavy quantity of computing, it's difficult to satisfy the real-time requirement by software. Therefore, it often makes use of hardware to satisfy requirement for speed in many practical applications. The purpose of the thesis is to implement 8×8 2-D DCT for image processing by hardware.The thesis introduces principle and function of DCT in image compression encoding at first, analyzes and studies various fast algorithms of DCT, summarizes the DCT fast algorithms and its VLSI implementation which have been done by previous researchers. Based on characteristics of image process, combining DCT fast algorithms and hardware implementation, the thesis presents a way of DCT hardware implementation. To overcome the synchronization problem in VLSI's design, the paper analyzes and compares the designs of asynchronous inputs, clock circuits, static hazards and race conditions. With the analytic results, we have given effective methods to ensure that the design is stable. Lastly, the thesis introduces the design of 2D-DCT hardware implementation particularly, based on the fast algorithm of using Looking up ROM tables. In order to improve the speed, the whole structure uses the parallel and pipeline in the computation cell. At last, synthesis and verification for design have been done. The result shows that the design could perform the function of 8×8DCT under 125MHz clock frequency. Total area is about 1403819.625000 um2 with 0.18 technology library of SMIC.