Resarch On Recursive Imdct Algorithms And Design Of An Audio DSP Core

The inverse modified discrete cosine transform (IMDCT) is one of the key techniques in audio decoding. Since it is computationally intensive, the IMDCT has significant effect on realizing real-time audio decoding. The recursive IMDCT algorithms have been thoroughly investigated since they are applicable to a large set of audio standards. In addition, the recursive IMDCT algorithms are suitable for very large scale integrated (VLSI) circuits implementation in parallel mode. Three recursive IMDCT algorithms and their hardware accelerator structures are presented in this work. Compared with one of the well-known recursive IMDCT algorithms, the three presented algorithms reduce the computational cycles greatly. To accurately evaluate the efficiency of the proposed IMDCT algorithms and investigate the audio decoding techniques based on an audio digital signal processor (DSP) core, a 24-bit audio DSP core is designed and verified by decoding AC-3 audio in real time in this paper.Based on the graduate investigation on recursive IMDCT algorithms, several noval IMDCT algorithms and their hardware accelerators have been implemented. Eventuraly the most efficient IMDCT algorithm and the acurrate hardware accelerator are realized in the 5.1 channels AC-3 real-time decoding. The results of this dissertation are listed in detail as follows:(1) A new decomposition algorithm of type-IV discrete cosine transform/type-IV discrete sine transform (DCT-IV/DST-IV) and architecture of a hardware accelerator for realizing fast inverse modified discrete cosine transform (IMDCT) computation are presented. Compared with two reported fast IMDCT algorithms, the proposed algorithm possesses the advantages of higher computational efficiency and simpler hardware implementation. A real-time audio decoding experiment was performed to verify the efficiency of the proposed algorithm. Experimental results show that 38% computational cycles are saved compared with one of reported fast algorithms for 512- point IMDCT computation.(2) In order to save hardware resource, a compact hardware accelerator structure for realizing fast inverse modified discrete cosine transform (IMDCT) computation is proposed. According to the previously proposed DCT-IV/DST-IV decomposition algorithm, the computation of IMDCT is coverted to the computation of DCT-IV/DST-IV. After transformation of DST-IV to DCT-IV, the DCT-IV/DST-IV is transformed into DCT-IV/DCT-IV. To obtain a compact hardware accelerator structure, a simple recursive DCT-IV structure is adopted. By changing the window values relavant to the IMDCT computation, the compact hardware accelerator structure is further simplified. Compared with the previously proposed hardware accelerator structure, the derived structure reduces 2 multipliers and 2 latches.(3) A new fast inverse modified discrete cosine transform (IMDCT) algorithm and an efficient hardware accelerator architecture are proposed. The proposed fast algorithm stems from our previously presented type-IV discrete cosine transform/type-IV discrete sine transform (DCT-IV/DST-IV) decomposition algorithm and absorbs the low latency virtue of another fast algorithm. Through elaborate manipulation, we get the formulas suitable for resource sharing and multiplexing. Experimental results show that the proposed algorithm's computational cycles for computing a 512-point IMDCT are decreased by 20% and 51%, respectively, compared with two other reported fast algorithms. The resource of the proposed hardware accelerator is reduced by 24% and 48%, respectively, compared with two other reported accelerators.(4) A new multi-decomposition algorithm for fast IMDCT computation and its corresponding computation-accurate accelerator structure are proposed. Based on the idea of multi-decomposition, four pairs of N/16-point DCT-IV/DST-IV are derived from a new decomposition method. Experimental results show that the computational cycles of the proposed multi-decomposition algorithm are decreased by 11%, 29% and 56%, respectively, compared with three other reported recursive IMDCT algorithms. Simulation results show that computing IMDCT using the proposed multi-decomposition algorithm and its hardware accelerator can meet the signal-to-noise ratio (SNR) requirement of Group C AC-3 decoder.(5) A 24-bit audio DSP core is designed and its FPGA prototype is verified by real-time AC-3 decoding experiments. In order to realize real-time AC-3 decoding, optimized decoding algorithms such as the multi-decomposition IMDCT algorithm and Goldschmidt divider algorithm are adopted. The IMDCT hardware accelerator and bit- parsing module etc. are added into the audio DSP core. Experimental results show that the proposed audio DSP core can decode the AC-3 audio (5.1 channels, 48 KHz and 448 Kbps) at 33MHz. The frequency of 33MHz is close to 27MHz at which the high performance DSP (TMS320C62x) decoded the AC-3 audio (5.1 channels, 48 KHz and 448 Kbps). Evaluation results show that by adding the hardware accelerators into the audio DSP core, the ratio of performance to cost is almost increased three times when the AC-3 audio is decoded by the proposed audio DSP core. Compared with the results from a commercial AC-3 decoding tool—AC3Tools Pro, the AC-3 decoding results from the proposed audio DSP core can abtain 1.91-13.9dB higher signal-to-noise ratio (SNR).