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Research Of Video Image Acceleration Modules

Posted on:2006-05-25Degree:MasterType:Thesis
Country:ChinaCandidate:X M LiFull Text:PDF
GTID:2168360152990767Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
The thesis includes two parts: the research for implementation structure of efficient two-dimensional (2-D) discrete cosine transform and inverse discrete cosine transform (DCT/IDCT) and image post-processing (Deblocking).The discrete cosine transform is one of the important tools in signal processing and image/video processing, which is accepted by several international standards, such as JPEG, MPEG, H.263. The precondition for using DCT in practical system is the algorithms for fast implementation of DCT existing. Since the first true DCT fast algorithm for DCT is proposed in 1977, looking for the faster, more structured and simpler algorithm for DCT is one of research topics in signal processing fields. This thesis proposes an efficient two-dimensional 2-D DCT/IDCT design. Adopting the row-column decomposition technique for computing 2-D DCT/IDCT, we formulate the one-dimensional (1-D) DCT/IDCT into cyclic convolution by properly arranging the input sequence, optimize the multiplications based on the concept of common subexpression sharing, and carry out the multiplications through carry-save adder (CSAs). Using cyclic convolution is helpful in exploiting the word-level data sharing in computing different DCT/IDCT outputs. Adopting the common subexpression sharing is beneficial to the bit-level data sharing in computing the outputs. Compared with some existing DCT/IDCT designs, the proposed design is distinguished in algorithm and implementation.Deblocking is a kind of image post-processing technique largely used to remove coding artifacts and improve the visual quality. The algorithm used to achieve these tasks is computationally intensive and usually require high speed processors to be able to run in real time. The thesis presents a deblocking filter architecture recommended by MPEG-4 standard. This architecture supports two separate filtering modes, which are selected by pixel behavior around the block boundary. In each mode, proper one-dimensional filtering operations are performed across the block boundary along the horizontal and vertical directions, respectively. In the first mode, corresponding to flat region, a strong filter is applied inside the block as well as on the block boundary because the flat regions are more sensitive to the human visual system (HVS) and the artifacts propagated from the previous frame due to motion compensation are distributed inside the block. In the second mode, corresponding to other regions, a sophisticated smoothing filter, which is based on the frequency information around block boundaries, is used to reduce blocking artifacts adaptivelywithout introducing undesired blur. Even though the proposed deblocking filter is quite simple, it improves both subjective and objective image quality for various image features.
Keywords/Search Tags:Binary signed digit representation, common subexpression sharing, cyclic convolution, discrete cosine transform(DCT), image compression, inverse discrete cosine transform (IDCT), block-based coding, blocking artifacts, deblocking
PDF Full Text Request
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