The Hardware Configuration Of Discrete Cosine Transform Based On Distributed Algorithms

Discrete Cosine Transform is wildly used in coding and decoding of image processing, which has been used by many international standards such as JPEG, MPEG1, MPEG 2, MPEG 4, H26X and so forth. Because of its high computing, software can not meet with the requirement of real time process. Therefore, we advise adopting DCT process circuit to satisfy with the requirement of the speed for processing, due to strict circumstance. The content of this thesis is that 8*8 DCT IP code for hardware implementation.This thesis introduce the role and principle of discrete cosine transform DCT and briefly elaborate the process the image transform using DCT method, and then comprise with other transform to specify advantages for image transform using DCT transform. Furthermore, it specifies different DCT method, and then summarizes DCT high speed algorithm and the characteristics for VLSI implementation. According to characteristics of image process and IP design idea, DCT algorithm and hardwire implementation, this thesis introduce one DCT hardwire design to increase speed and minimize design areas and power.In this method, we adopt DCT column-row character, using 6 pipelines design, then transform 2-DCT into 1-DCT, column and row method. In 1-dct design, we use DCT cosine coefficients and by making use of its rotation characteristic, multiplication function can be designed by shift and addition logic instead of direct multiplication unit by which can save design resources while improve the speed. At last, synthesize and verification for design has been done. The result shown that the design could complete the function of 8×8DCT under 100M clock frequency.