Research And Hardware Design Of Discrete Cosine Transform

Discrete cosine transform (DCT) and the derived transforms like shape adaptive DCT (SA-DCT) and integer cosine transform (ICT) are adopted by the mainstream video standards like MPEG-2, MPEG-4 and AVS. In this paper, an in-depth study is made on these three transforms, and some new algorithms and their corresponding architectures are proposed.First, distributed arithmetic (DA) and a specific accumulator are used in the design of DCT to achieve a high throughput up to 8 pixels per clock, which is suited for high definition video compression application. Second, for the design of SA-DCT, booth encoding is introduced for coefficients of DCT, and the design concept of programmable processor is adopted to computing various-length DCT while a novel transposed register array is proposed to implement the transpose operation necessary for SA-DCT. The proposed SA-DCT core costs about 12500 gates with the maximum power consumption of 2.54mW. Third, a more simplified structure with 6 adders is proposed to implement the algorithm based on ICT (10, 9, 6, 2, 3, 1) which is invented by W.K.Cham.Besides the derivations of the algorithms, the design ideas,architectures and performance comparisons are shown in this paper as a good reference for other designers.