Research And Design Of Relevant Modules In HEVC Encoder

With the increasing requirement of video resolution, the amount of information contained in each frame of a video increases sharply. Although large-capacity storage devices and high-bandwidth transmission equipments to some extent alleviate video storage and transmission, the gap between the video storage and transmission requirements and the technical level is becoming more obvious. Aiming to compressing the original video coding, video coding technology can solve the video storage and transmission problems fundamentally, moreover, video coding standard needs constantly updating to meet the compression requirements of increased video information. It can be said video coding technology innovation promotes the development of the consumer electronic industry. As the state of the art video coding standard, HEVC’s (H.265) compression performance is about twice of the preceding video coding standard (H.264/AVC). However, the current HEVC also brings increased complexity in terms of software and hardware implemention while achieving the established compression objectives, thereby reducing the coding efficiency. In this paper, In order to simplify HEVC implemention and improve coding efficiency, we design several modules in HEVC encoder optimally.The main work includes the research and design of the several following modules in HEVC:(1) for transform module, we propose a HEVC integer discrete cosine transform implementation architecture based on the theory of stochastic computation. HEVC uses fixed-point integer transform technology, which brings complex integer multiplication and addition operations by direct implementation, while stochastic computation can convert arithmetic operations to logic operations to reduce the complexity of arithmetic with tolerable computing error. Based on this, we propose an integer discrete cosine transform method base on theory of stochastic computation, and then propose an improved accuracy structure furtherly in terms of computing error. What’s more, we implement the butterfly architecture of HEVC integer DCT and take it as an anchor, Simulation and FPGA implemention results indicate that the proposed architecture can archieve HEVC integer DCT with less half and twice of the anchor in terms of hardware resourece and working frequency respectively (2) for entropy coding module, we propose a HEVC CABAC implementation architecture based on an efficient4-stage arithmetic coding pipeline structure. Starting from the analysis of key point of HEVC CABAC hardware implemention, we propose an improved pipeline division structure. We also propose a context access model based on cache for the conflict problem in context access processing and an optimized low updating and byte-output structure based on characteristics of renormlization. Finally, simulation and implementation results of HEVC entropy coding hardware implementation show that the proposed architecture can archieve throughput of417Mbins/s and meet real-time encoding of4K videos (3) for intra prediction module, we propose a fast decision of coding unit (CU) partition algorithm based on entropy of image co-occurrence matrix. HEVC recursive adopts a time-consuming rate-distortion optimization (RDO) technique to partition CU exhaustively. In this paper, through the study of the final division rules for encoding unit, we propose a fast CU partition method based on characteristics of co-occurrence matrix, which can reduce26%and gain1%in terms of encoding time and bit rate respectively compared with the HEVC test module (HM).