Research On Dynamic Hardware/Software Partitioning Methodology Based On Pre-configuration In Functional-Level

As the embedded electronic products become smaller and smaller, more and more designers are using Reconfigurable System-on-Chip (RSoC) technology in the embedded system design, and the research on hardware/software (hw/sw) co-design for embedded system are focusing on the hw/sw co-design on RSoC. Since the RSoC includes the microprocessor and the programmable logic device, mapping functions into these two types of computing units efficiently is very important in hw/sw co-design for RSoC. Research on dynamic hw/sw partitioning for RSoC can help to make full use of the advantages of RSoC to achieve highly efficient embedded applications. This thesis studies pre-configuration strategy and dynamic hw/sw partitioning algorithm based on reconfigurable computing technology. The main contributions are outlined as follows:1. A new pre-configuration model based on dynamic partial reconfiguration is proposed for mapping abstract functions, using Directed Acyclic Graph (DAG) as the system description. The execution of the abstract function is divided into configuration and computing. We try to hide the configuration time of an abstract function into the executions of other abstract functions through pre-configuration. After we finish the calculations of configuration time and execution time, we use a pre-configuration strategy based on Pre-Configuration Time (PCT) to make a pre-configuration scheduling. Experimental results show that the scheduling can reduce the reconfiguration cost compared with the scheduling without pre-configuration.2. A hw/sw transparent programming model is presented to hide the details of the reconfiguration hardware to the programmer. A dynamic hw/sw partitioning algorithm is proposed with the granularity at the function-level to automate the choices of hardware or software implementations of the abstract functions. With consideration of the resource constraints and the practical hardware status, a dynamic hw/sw partitioning algorithm in function-level with pre-configuration is implemented. Experiments show that the proposed algorithm is faster than the Simulated Annealing algorithm.Finally, a prototype system is implemented in Xilinx Virtex-4 FX FPGA platform, which has a library of hardware and software functions. Preliminary efforts are also made to combine the algorithms mentioned above in the prototype system. Experiment results show that the prototype system is able to map an application from system specification to the hardware/software implementation in function-level automatically.