Research And Implementation Of SoC-oriented Hardware/Software Partitioning System

The rapid development of microelectronics techniques promotes IC into SoC era, but with the increase of SoC design complexity, the conventional design technology can't satisfy the demand of SoC design. Hardware/software codesign is one of the key techniques that advance the development of SoC; hardware/software partitioning is the key problem of hardware/software codesign. So the research on this issue is of high academic and applied value.Now the platform based design methodology start to get widely used, hardware/software codesign technique is deeply affected by platform based design methodology. This paper study platform based design methodology and SystemC that is one of system level design languages, then this paper introduce the SOC-CDE environment. The SOC-CDE environment adopts platform based design methodology, design flow has three abstract design levels, include: algorithm level, virtual component level, real component level. Hardware/software partitioning belongs to the virtual component level design.This paper chooses Genetic Algorithm, study automated partitioning technique based on constraint programming and task programming. Depending on both the design programming and the GA's characteristic, this paper present an automated partitioning algorithm based on design programming. No less than what we expected, the algorithm can effectively search the solution space. The research of interactive hardware/software partitioning system is of applied value, this paper design an interactive HW/SW partitioning system. Interactive HW/SW partitioning system is based on virtual component level representation model, this model links the algorithm level design and virtual component design. The interactive partitioning system embody the platform based design character of SOC-CDE environment, and make good use of the design programming result in algorithm level.The HW/SW cosimulation is one of important techniques for the verification and performance evaluation of SoC design. For the need of hardware/software partitioning performance evaluation, this paper study the virtual component level HW/SW cosimulation techniques, and design a performance evaluation system based on the result of the virtual component level cosimualtion.