| As the demand of computing performance gradually increasing, high-performance computing faces many challenges. People begin to think over how to take efficiency into account as well as pursuing performance. High Productivity Computing is proposed under such a consideration. A reconfigurable computing system consists of not only micro processers which execute software programs, but also reconfigurable devices which implement hardware logic. In order to utilize reconfigurable computing systems efficiently, researchers came up with a totally new area, i.e. hardware/software co-design, which is used to fill the gap between design capacity and manufacture capacity.This thesis focused on the hardware/software partitioning problem and high- level synthesis technology among hardware/software co-design technologies. The main research and innovation include:1. Proposing a system architecture model facing loosely coupled reconfigurable systems. It consists of a general purpose processor and a reconfigurable processor, and they connect each other with a loosely coupled connection. The reconfigurable processor comprises a micro-processor and an FPGA, which connect each other with a tightly coupled connection. We adopt directed acyclic graphs as the system description model, and the total executing time of a program is determined by the executing time of nodes on the critical path and the communication overhead between these nodes. Since the communication overhead of a loosely coupled connection is much higher than a tightly coupled one, the model applies a reasonable simplification to the calculation of system communication overhead. C urrently, researchers mainly focus on embedded systems and tightly coupled reconfigurable systems. However, most large reconfigurable computers are loosely coupled at present. The proposed model of this thesis takes into consideration the portioning on all the three types of nodes within a loosely coupled system. Therefore, it is more representative of state-of-the-art large reconfigurable computers, being adaptable to the future research trend.2. Aiming to compensate the deficiency of the hardware/software partitioning algorithm facing loosely coupled reconfigurable systems and large task sets, a hardware/software partitioning algorithm called SATS is proposed which fuses simulated annealing algorithm and tabu search algorithm. Firstly, this algorithm uses simulated annealing algorithm, which is independent from the initial value, to partition the nodes on the crucial path of system DAG for several times, getting a better initial result. Then tabu search algorithm is applied on the initial result to get a global approximate optimal solution. Experiment results show that t he hardware/software partitioning algorithm facing loosely coupled reconfigurable system proposed by this thesis is suitable for solving the hardware/software partitioning problem under large task sets, and it has an obvious advantage on the execution time.3. Proposing a software communication support method called ECSPE for high- level synthesis, and implementing it based on CoDeveloper. ECSPE method applies Ethernet to implement the pipe in CSP model, using a reliable protocol to communicate between hardware and software processes. This method sets a consistent signature for a couple of hardware and software processes by computing the hash value of source codes, avoiding conflicts when several hardware/software programs execute in a local area network at t he same time. This thesis implemented ECSPE method on the high- level synthesis tool Co Developer in the form of platform support package. Several couples of hardware/software programs are written, and then they are tested on the PRCA prototype. The test res ults show that ECSPE method can fulfil the communication work between hardware and software processes, and conflicts are avoided when more than one couple of hardware/software programs execute at the same time. |
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