Simulation Verification And Test Scheme Design Of FRAM Read/write Circuit

With the advent of the information age,society’s demand for various components in the field of integrated circuits has grown rapidly.In the field of memory,China is in urgent need of a number of non-volatile high-speed memory.The good compatibility of ferroelectric materials with CMOS process and their excellent storage characteristics gradually make them become a research hotspot.The main purpose of this thesis is to simulate and test the read/write circuit of a ferroelectric memory chip by means of simulation and test verification.This thesis first introduces the basic principles of ferroelectric materials and the basic ferroelectric memory cell,and then explains the external and internal structures of this ferroelectric memory chip in detail.Then,the three key functions of the read/write circuit and several read/write modes of the overall circuit are verified by means of simulation,and the entire verification process is verified under various operating environments such as high and low temperatures to make its validation consistent with the environmental conditions of use.Of course,during the verification process,we also found that the following deficiencies still exist in the design of this memory: first,it is too cumbersome for the user to read and write,and second,there is redundancy in the read and write cycles of this memory.To address these two shortcomings,this thesis completes the optimization of the memory circuit and proposes a new read/write mode,that is sequential address change read/write mode,which not only makes the user’s read/write operation easier,but also improves the performance of this memory tremendously,reducing the read cycle to 50% of the original read cycle and the write cycle to 55% of the original write cycle.In addition,the page mode and the continuous address change read/write mode are combined to propose the continuous address change read/write mode within the page,which not only has the advantages of the continuous address change read/write mode,but also brings the advantages of the page mode into full play.Finally,combining March C-algorithm and common failure model analysis of memory,a complete FPGA test platform is built for the chip of this memory,and a detailed test plan and test flow is developed.In the simulation and verification process,this thesis has completed the verification of this memory chip from local to overall,from function to performance.In addition,the highlight of this thesis is not only the description of the verification process of this ferroelectric memory,but also the exploration of some new optimization directions for this memory in the verification process,and the design and verification of the optimized circuit,which finally makes the performance of this memory greatly improved.In the test process,the March C-algorithm is combined to make the whole test process include most of the possible failure models of the memory.