Design Of RRAM High Reliability Control Circuit For In-memory Computing

In today’s brand new information society,the need for information storage is becoming more and more important.At the same time,as people pay more and more attention to many emerging disciplines and research fields based on big data analysis,more advanced storage technologies are needed.They are needed to support the collection and storage of a large amount of target data,and provide strong support for the development of these disciplines and research fields,which also makes storage technology play a vital role in the development of integrated circuits.Aiming at the current bottlenecks faced by storage technology in terms of device physical characteristics,manufacturing technology and application requirements.This thesis compares and analyzes the advantages and disadvantages of several modern new non-volatile memories,and chooses Resistive Random Access Memory which is a new type of non-volatile storage technology with broad application prospects.And it is also taken as the research and design object of this thesis.Combined with the latest research results of RRAM at home and abroad,and its application in in-memory computing,the peripheral control circuit of this new type of memory device is deeply studied.The main research contents and achievements of the thesis are as follows:1.On the basis of in-depth research on the characteristics and working mechanism of RRAM resistive memory devices,the advantages and disadvantages of several resistive memory cells and array structures are compared and analyzed.And the 1T1R memory cell structure based on bipolar RRAM devices is determined according to the application requirements.Based on this,an RRAM storage array structure with a storage capacity of 1 Mb is designed,including the Main Area of data storage,the Redundant Area of operation information storage and the Reference Array.Based on the Speed-adaptive Resistive Model and the memory cell read-write mechanism,a behavioral model of the RRAM memory array is designed and implemented for the design simulation of the peripheral control circuit.And the simulation fitting results of the resistive model are consistent with the resistive characteristics of the actual RRAM cell.2.Aiming at the requirements of read and write reliability for in-memory operation data storage,the accuracy of RRAM read and write data is solved through peripheral control circuits,and corresponding read and write control schemes are designed,including a write verification scheme,a REC data recovery scheme and an Error Checking and Correction mechanism.Among them,the write verification scheme ensures the reliability of data writing by controlling the verification interaction between the data to be written and the stored data.The REC data recovery scheme solves the read interference effect of the RRAM memory cell,and helps to improve the resistance uniformity of the memory cell,increasing the high and low resistance state read and write windows.The Error Checking and Correction mechanism ensures the reliability of data reading by performing verification and error correction on the original stored data and read data.3.The overall structure of the RRAM peripheral control circuit is determined.And the RRAM peripheral control digital circuit based on the SPI serial communication protocol is designed,including input and output circuit,instruction decoding circuit,status register,address decoding circuit,write control circuit,read control circuit,REC data recovery circuit and ECC check control circuit.Among them,a set of RRAM SPI operation instructions are designed based on the RRAM storage mechanism and functional configuration to control the operation of the main control logic state machine.The address decoding circuit is designed based on the address mapping relationship of the distributed data storage mode.The write control scheme adopts the state machine implementation method to complete the design of each operation state machine of the main control logic.The ECC check control circuit is designed and implemented based on the RRAM Error Checking and Correction mechanism.4.According to the SPI command input format and design specification,the simulation incentive is formulated.And the function simulation of the whole circuit is carried out to verify the correctness of the design function.In terms of reading and writing reliability improvement,the write verification optimization design achieves high and low resistance distribution variances of 1.6 and 0.8 respectively.The REC optimization design achieves100%data recovery rate,and the recovery high resistance distribution variance is 1.3.ECC optimization design achieves detection and error correction 1 bit function.The results show that the overall reliability improvement goal is completed.Finally,based on the SMIC 130nm process,the logic synthesis of the RRAM peripheral control digital circuit is carried out,and the integrated circuit area is 80719.8μm~2,and the power consumption is 4.17 m W.Formal verification is carried out on the gate-level netlist after synthesis and the original RTL-level design.The verification result shows that the function of the synthesized circuit netlist is correct and meets the design requirements.