LDPC Encoder And Decoder For DTMB And Their FPGA Implementation

Low-Density Parity-Check(LDPC) codes are excellent error-correcting codeswith performance close to Shannon limit.For long code length,it can even outperformTurbo codes. LDPC codes are adapted for high speed hardware implementationbecause of its low encoding and decoding complexity especially for quasi-cyclicLDPC codes.Now LDPC code has been adopted as the Error-Correcting scheme in thefourth generation mobile communication systems. Channel coding adopts LDPC codeas its inner code and BCH code as its outer code in DTMB (Digital Terrestrial MediaBroadcasting) standard.The utility value of hardware implementation about LDPCencoder and decoder is great because of high speed requirement for digital TV.In this paper, the encoding and decoding algorithms are analyzed, then thedecoding algorithm and its message-passing schedule which are most suitable toLDPC decoder are searched by performance simulation. The key parameters aboutdecoding algorithm are also confirmed by simulation. With all the work of abve, theencoder and decoder are implemented in FPGA, and ameliorations are proposed inorder to reduce the use of logic and memory resources when the throughputrequirement in DTMB is matched. Lastly, the encoder and decoder are implement onXilinx XC4VSX35FPGA, the timing simulation and test on board are also completed.The capability anlysis indicate the throughput requirement in DTMB systems ismatched.The main contributions and innovations in this thesis are as follow:1. An LDPC encoding architecture is proposed whose output format iscontrollable. This encoder can be chosen in different output formats according to fivedifferent symbol-mapping patterms in DTMB standard so as to provide the optimaldataflow width, which improves the generalization of encoder.2、A new decoder architecture is proposed to solve the problem of huge resourcesuse in traditional LDPC decoder, which needs less logic resources and memoryresources by dividing submatrix to improve serial factor of decoder.3、 In order to make full use of BlockRAM in FPGA, a special storing scheme isadopted in LDPC decoder which fits the long and narrow BlockRAM architecture best.4、A permute network based on barrel shifter is adopted to submit message inLDPC decoder which avoids high complexity from hardware connection.