Design Of Low Power 10-bit A/D Convertor With I~2C Interface

ADC as the connecting point between the analog world and digital world,it plays an indispensable role in the field of signal processing,now it is widely used in the systems on chips(SOC).Along with the advance of information technology,especially rapid developments of the portable electronic equipments,automotive electronics and the signal acquisition devices with battery power,so the demands for small volume,low power become increasingly stronger.Compared to other kinds of ADCs,SAR ADC has the advantages of simple circuit structure,low cost and low power consumption.In order to let the electronic equipments with low voltage power supply complete A/D conversion better,SAR ADC is the best choice undoubtedly.In this paper,a 10-bit SAR ADC based on I~2 C bus interface is been proposed,this chip can work on the standard mode and quick mode of the I~2 C bus,and completes the analog-to-digital conversion and data output according to the instruction of microprocessor.The traditional digital coding parallel output pins are replaced with the two I~2 C bus interfaces,this reduces the number of the chip pins,and make the occupied area on chip become decreased significantly.This paper emphatically analyzes the circuit designs of DAC and comparator.For the DAC module,a 12-bit DAC designed with three-stage different scaling types piecewise combination is proposed,using high precision characteristic of capacitance and monotone feature of resistance string partial pressure improve the accuracy of D/A conversion.The method of piecewise combination reduces the number of unit devices in weighted network significantly,and reduces the DAC's power consumption and layout area effectively.For the comparator module,a pre-amplifier and latch cascade comparator with offset zero suppression is proposed,this cascading way not only increases the gain of the comparator and enhances the resolving power of this comparator,but also reduces the transmission delay of the comparator.By the output disturbance elimination technology,eliminates the interference of offset voltage.Then this paper shortly introduces the Sample-Hold circuit,SAR registers,oscillator circuit and I~2 C logic module circuit,analyses their working principles and specific functions.Under the Linux system,using the simulation software Cadence IC 5.1.41 finish the whole system circuit design,and using Cadence Spectre and Matlab to simulation analyze and verify each module circuit and the whole system circuit.The simulation results show that the ADC chip can accurately complete the A/D conversion and output the digital coding by the I~2 C bus,the maximum integral non-linearity distortion is-0.43 LSB,the maximum differential non-linearity distortion is 0.21 LSB,the effective digit is 9.37 bits,the whole power consumption of the SAR ADC chip during A/D conversion is 1.132 m W,so this SAR ADC has great advantage in the field of low power applications.