Design And Implementation Of Boundary Scan Test System For Complex Digital Circuit Board

As the manufacturing process of integrated circuits is more and more developed,the traditional probe fault detection methods can not meet the fault detection requirements of such boards.The boundary scan test technology is proposed to solve large complex electronic devices such as VLSI.However,the traditional boundary scan test technology is also insufficient with the development of integrated circuits.This paper analyzes the application of the current boundary scan test technology,and combines the characteristics of complex digital circuit boards to analyze the current boundary scan test technology in complex digital circuits.In the application of the board,there are shortcomings and shortcomings such as long scan chain,low test efficiency and low test coverage.Therefore,in order to better meet the fault detection requirements of complex digital circuit boards at present and later,this paper based on these shortcomings and shortcomings.In this paper,based on the complex digital circuit board boundary scan test technology,a boundary scan test technology suitable for complex digital circuit boards is proposed.The main research contents are as follows:1.A new scanning chain design method is proposed.In this paper,the scanning chain design method of "divide and conquer" is proposed for the shortcomings of current design.This method obtains the main scan chain and the secondary function scan chain by classifying and processing the chips on the complex digital circuit board.In the scan test of the scan chain,the scan area of the secondary function scan chain is obtained,and then the scan scan of the secondary function scan chain is performed,and finally the fault is located to obtain the fault information existing on the complex digital circuit board.2.Design and implement a boundary scan controller.In this paper,the design method of the current boundary scan controller is analyzed and compared.It is found that the current design method has the limitations of the data transmission speed receiving interface,the large amount of method programming,and the complexity of the system.After summarizing these shortcomings,The FPGA and SN74ACT8990 bus control chip are used to design the boundary scan controller.This controller combines the data processing capability of the FPGA.At the same time,due to the use of the existing bus control chip,the system design is simple and the JTAG bus signal can be easily generated.Perform a boundary scan test.3.Design and implement a boundary scan software interface.After completing the hardware part of the boundary scan test system,this paper designs the boundary scan upper computer control software for the scanning system test method designed in the paper.The functions included in the software are: automatic test of test vector,information display of test fault,Selection of test circuits and information display of board faulty devices.In this paper,the boundary scan test system is verified by the upper computer software interface to prove the feasibility of the boundary scan controller and scan chain designed in this paper.