Design And Implementation Of TS Over IP System Based On FPGA

This dissertation designed a kind of TS over IP system, The MPEG transport stream is knownas the TS. TS mainly transmit through ASI in traditional television network. Put forward of "tripleplay" strategy in our country, makes further the development of network television, IPTV andOTT TV began to emerge and gradually gained popularity. Because of IPTV and OTT TV aresystems through which television services are delivered using the Internet protocol suite, so weneed a device which can switch TS flow to IP packet. It is known as the TS over IP system.This dissertation designed and implemented a kind of TS over IP system based on FPGA andPHY chip. It consists of three parts in FPGA, the R8051XC2which be treated as the primaryprocesser, the TS module, and the MAC module.TS module is comprised of TS interface and data buffer. The functions of the TS interface arereceiving the TS data from the SPI and ensuring the integrity of the TS data. The data buffer iscomprised of read/write control module and dual port RAM. It implements the continuoustransmission of data.The functions of the MAC module are implementing the media access control andcommunicating with the PHY chip. It is comprised of sending and receiving buffer and EMIF.The TS module and the MAC module are treated as peripherals that mount on the EMIF.R8051XC2can accesses the two modules because they are allocated to the different address space.The two modules can also communicate through the DMA based on the DMA controller inR8051XC2.There are two clock domains in this system, the frequency of one of them is27MHz and theother is100MHz. And there are also two clock domains in MAC module, one is100MHz and theother is25MHz.So an improved Handshake Protocol based on interrupt is designed in thisdissertation to solve the problem of communication between the different clock domain.The system designed in this dissertation uses RAM as the data buffer that is different fromthe traditional system which uses FIFO as the data buffer. This dissertation design a new methodto encapsulate the TS data using the feature that RAM can read-write the specified memory cellaccording to the address line. It reduces the number of roundtrips and the requirement of thehardware and improves the efficiency and cost performance of the system.