The Design Of EMIF Interface Based On DSP

PCI(Peripheral Component Interconnect)bus is a kind of bus structure which combines the peripheral device with the processor for the high speed.It has become the most popular computer local bus with its excellent technology,rich functions and excellent performance.External memory interface(EMIF)has a strong ability to interface,not only has a very high data throughput,but also can be directly interface with the current almost all types of memory.All kinds of equipment which support PCI bus has a wide range of applications,but in the domestic,PCI bus related products are in the state of exploration and research,and its products are not much.Therefore,PCI main controller IP core has a very high value.On the basis of deep research on PCI protocol and EMIF interface signal and its characteristics,base on DSP TMC320C6713 External memory interface designs hardware system architecture,partitions modules and sets the data interface of IP core and data packet format based on functional requirements of encryption IP core,Detailed elaboration is also given to the functions of the key module,structure and circuit design.Then,the Verilog hardware description language is used to design the RTL(Register Transfer Level)of each module,and the function simulation is completed.Finally,the EMIF to PCI main controller is complete which realizes the various function.Results show that the design has the standard EMIF,PCI bus interface,EMIF interface protocol support,using a 26 bit address bus and 32-bit data bus,PCI bus interface protocol support,using 32-bit address bus and data bus,the main system clock to 66MHz,achieve the expected performance index.This design through the EMIF expansion on the market to have the function of SOC circuit,can make full use of existing resources,effectively reduce the development cycle,saving the development cost.In order to further research and development of our country with independent intellectual property rights and the design of the international general standards of the important IP combination of reference and exploration.