Study Of Asynchronous On-Chip Communication Link Techniques Based On GALS NoC

With the development of integrated circuit process, more and more complexfunctions can be integrated into one chip. The synchronous MPSoC and NoC face seriesof issues such as clock skew, clock jitter and power consumption caused by the globalclock signal. The global asynchronous and locally synchronous (GALS) design methodhad been proposed and become effective way to design high-performance MPSoC,especially for NoC. The GALS integrate asynchronous IP cores and synchronous IPcores. The modules in asynchronous IP cores use asynchronous pipeline as dataprocessing and transmission link. The synchronous IP cores translate the synchronousdata into asynchronous data via wapper. The IP cores use asynchronous on-chipcommunication link to communicate and exchange data. Thus, the asynchronouspipeline and asynchronous on-chip communication link based on different protocols andways will have an effect on the performance of the GALS NoC. This thesis mainlystudies on-chip communication link with data processing in asynchronous IPcores, anddata transmission on-chip communication link between IP cores. The contributions ofthis dissertation are as follows:1. The pipeline based on parallel completion is proposed to resolve the throughputand power of four-phase dual-rail pipeline. The series-parallel ways improve thethroughput of the pipeline. Moreover, the static power of the pipeline in NULL cycledeclines as well because of the new threshold gates. The proposed pipeline can be usedto design communication link with data processing function in asynchronous IP.2. This thesis proposes a delay-independent asynchronous dynamic priority arbiterfor communication conflict. In an arbitration period, by comparing the priority of thedata packets with request signals, the arbiter will output the data packets in the sequenceof descending priority. The packets with equal priority are outputted serially. The arbitercan be used to avoid communication conflict in on-chip communication links.3. The paper firstly studies protocol interface in communication link, innovativelypropose protocol converters between four-phase dual-rail protocol and dual-railsingle-track protocol, four-phase bundled protocol and dual-rail single-track protocol, aswell as two-phase LEDR protocol and dual-rail single-track protocol, in order toimprove flexible usage of these two types protocol.4. This paper proposes a novel elf-acknowledgement high-speed asynchronousdual-rail push channel for long-range data transmission on-chip communication link. The asynchronous channel transmits dual-rail data through two independenttransmission link in order to avoid complex timing design, reduce transmission linkinterference. Meanwhile, based on proposed protocol converters and asynchronousself-acknowledgement channel unit, the two-phase self-acknowledgement asynchronouson-chip communication link has been designed. The two-phase self-acknowledgementasynchronous communication link can communicate with traditional asynchronous linkby changing protocol interface. Compared with two-phase LEDR communication link,the two-phase self-acknowledgement asynchronous communication link is superior interms of throught, power dissipation and area.5. The self-acknowledgement asynchronous serial communication link, which cancommunicate with current asynchronous protocol, has been proposed to optimize area,power dissipation and interconnect resource. Simulation results have shown that theserial communication link has lower power consumption, a smaller die area and fewerinterconnects than the self-acknowledgement bit-parallel link. The serialcommunication link can save interconnect resource, reduce crosstalk and improvecommunication reliability, which can be used in low-power on-chip communication.