Research On Asynchronous Integrated Circuits Design Methods

With the development of VLSI, along with access to deep sub-micron CMOS process technology, IC designers are more and more increasingly troubled by the design of clock tree, which hence led to more and more attentions to IC designers.Since the development of asynchronous IC design is very slow, and the design system is as consummate as it is in synchronous IC design system, it is far more complicate for asynchronous design than synchronous design. If we can achieve a set of theories to directly change synchronous algorithm or codes into asynchronous chips, this would definitely allows rapid induction in asynchronous IC design. Based on this concept, a lot of people in this professions committed to the study, and obtained plenty of results, but only limitied to pipelined algorithm conversion. This paper also implemented a conversion method, which not could only convert pipeline structure algorithm, but also proposed an idea of state machine structure algorithm convertion. In this paper, the works finished and main innovations are as followed(All designs and simulations are achieved under completely synchronous IC design environment):1. Based on the reaserch of asynchronous handshake protocols, I independently designed asychronous controllers in two main structure, which is pipeline structure and state machine structure. In the design of pipeline asynchronous controller, based on redundant four phase bundled-data protocol, we improved it into a quasi-symmetric de-dual asynchronous controller. Pipeline structure asynchronous controller composed of this quasi-symmetric de-dual asynchronous controller could completely eliminate reduction of the throughput of the pipeline due tu the dual defect inherent in the asynchronous handshake protocol. In the design of state machine structure asynchronous controller, we independently proposed and implemented a method, which could implement state machine structure asynchronous controller completely under synchronous VLSI design environment. And, we also deisgned a pulse generator module and add it into the controller design, which would reduce the width of the enable signal for latches and thus reduced the requirement of hold time constraints.2. At first we start with 128-bit(64-bit×64-bit) high-performance multiplier based on radix-4 Booth algorithm and 4-2 compressing algorithm. Combined with the quasi-symmetric de-dual asynchronous controller we designed, we design and implemented a 3-stage pipeline structure asynchronous multiplier, with correct pre-simulation results and post-simulation results. Under full flow operation, the speed of this module is more than 37 MHz, which could be further improved with more delicate pipeline division.3. Then, combined with the quasi-symmetric de-dual asynchronous controller we designed, we designed and implemented a module with more complicated algorithm, which is DES encryption module with 16-stage pipeline structure. We also achieved correct results in both pre-simulation and post-simulation. The speed of this module under full flow operation is exceeds 50 MHz.4. And then, combined with the quasi-symmetric de-dual asynchronous controller we designed, we designed and implemented the international general secure chip algorithm -- Advanced Encryption Standard(AES) in pipeline asynchronous structure, for which we implemented both encryption module and decryption module in four kinds of stage divison -- 2-stage pipeline, 3-stage pipeline, 5-stage pipeline and 10-stage pipeline. Which enabled us to analyse and research in the effction of different stage division on area and speed.5. At last, combined with the state machine structrue asynchronous controller we designed, we implemented a 32-bit(16-bit×16-bit) state machine structrue multiplier. The reason for the choosing of low bit module is that more bits would only introduced to operation complication and little algorithm complication. Pre-simulation results shows this design method is practicable. And we also have introduced early termination strategy into this design and obtained right simulation results.