The Optimization Research Of Cache Sub-system Based On SPARC V8Architecture

With the development of computer technology, and the progress ofmicroprocessor, the need of processor extends from high performance intoanywhere in our life. And the need of embed processor for special use is more andmore big.With the development of microelectronics, it make the dimensions oftransistor is more and more small, and the speed is more and more fast, thefrequency of the processor is more and more fast. Because the improvement of thememory is slow, memory becomes a bottleneck of computer system performance.To improve the performance of computer system, researchers have proposed thestructure of the memory system. Cache is a very important part of memory system.This article is base on the embedded processor which implements SPARC V8architecture. A cache subsystem, including instruction cache, data cache, and theinterfaces to processor and memory, is built up in the article for special applicationenvironment.The cache performance is evaluated when the cache is fulfilled with differentsize, set, and line size. According the result, an optimal structure is selected.Furthermore, the instruction cache’s behavior is studied. The instruction Cacheis stopped of filling if a branch instruction is executed in the process of instructionCache filling. The method can reduce unnecessary instruction filling, thus increasethe CPU performance by4%.The write operations of data cache with write though policy is low efficiency,thus a4words deep write buffer is produced. The CPU can execute one writeoperation in one circle if the frequency of write operations is normal. Theconsistency of data Cache and main memory is guaranteed by snooping the AHBbus.At last, stimulates are produced according to the behavior of Cache. Thestimulates are used to verify the Cache subsystem. VMM is used to analyze thecoverage, and the function coverage is100%.