Software Optimization Techniques For Small Instruction Caches

With the progress of integrated circuit manufacturing processes and computer architecture, the gap between processor and memory’s speed is also growing, the speed of reading the instruction has a significant impact on processor performance. So how to improve the performance of the instruction cache, improving processor performance has become the focus of study. Especially in low-cost embedded processors, with small-capacity caches, instruction cache hit rate has significant impact on performance.According to the characteristics of small-capacity cache miss, this paper presents several methods to optimize instruction cache in software way. Instruction cache software optimization techniques, based on statistical analysis by using gcov and gprof tools, which can reduce computational complexity in the process of optimization are proposed.PH algorithm and cache coloring algorithm do not take cache size, program size, and cache block size into account. When the subroutine size is close to or bigger than cache size, the optimized result is poor. So this paper presents optimized cache line coloring algorithm, which splits the big subroutine before coloring and sorting. Also a formula "Cache Locking Selection Sorting" is proposed to evaluate the code segment which should be locked or non-cached. Simulations show that these techniques make the program running time reduced by8%, make the cache hit rate increased by23%. The effect is significant.