Research And Design Of Instruction Cache In Cost-effective DSP

System throughput is an important measure of the performance of a processor,and system throughput is often limited by CPU performance.Research shows that the difference between the price of a fast memory chip and the next fastest speed grade can range up 50% or 100%,but the memory can only gain an extra 20% in speed,unfortunately this can not get the corresponding Ascension in speed in the CPU.So in order to design a cost-effective DSP processor,Cache design has become a key factor in improving the performance of the processor system.Cache research has become the current DSP processor development in a hot topic.This paper is mainly for 32-bit fixed-point DSP processor AXP32(AXP32 clocked at up to 150 MHz,peripheral frequency up to 40 MHz),and put forward the "two-level cache" structure design.In order to improve the speed of CPU fetch the instruction from external memory,between CPU and external memory inserted a instruction Cache,this is the "first level cache." The instruction cache design capacity of 512 B,block size of 16 B,the mapping rules for the direct mapping,according to the basic process of digital IC design,the instruction cache is divided into two modules: the data part and the control part.The data part mainly implements the function of finding and comparing,and the control part realizes the next step of the instruction cache according to the search result."Second-level cache" is designed based on plug-in SPI FLASH,in order to improving the communication speed between the DSP core and external FLASH,inserted an asynchronous FIFO.The asynchronous FIFO uses the Gray code counter to synchronize the read and write pointer,and the read and write address generation logic,the empty flag judgment logic is designed and explained in detail.In the design of this article,the Verilog programming language is used to implement the RTL level of the design of the subject,and the function of the instruction cache and the asynchronous FIFO is simulated by Cadence's NC-Verilog simulation tool.The simulation is followed by the use of Synopsys' Design Compiler synthesis tool to optimize the design of the code.The synthesis results are as follows:the total output of the instruction cache is 0.351 mm2,the power consumption is 38.85 mW,the clock frequency is up to 150 MHz;the total area of the asynchronous FIFO is 0.011 mm2,the power consumption is 452.95 ?W,the read clock frequency can reach 100 MHz.