Architectural Level Leakage Power Optimization For Cache Memory In Microprocessors

As the development of the IC manufacture technology, especially as feature size shrinks into the deep sub-micron and ultra-deep sub-micron generations, the power issue is more seriously and becomes the main obstacle and challenge for improving the performance of microprocessors continuously. Specially, the leakage power will exceed dynamic power and becomes the most important factor for microprocessor design. Obvious leakage power will not only increase the microprocessors' energy consumption and the manufacture cost, but also influences the microprocessors' stability and credibility. The leakage power in on-chip cache memory is the main component of the leakage power in whole microprocessor. So, decreasing the leakage power in on-chip cache memory is the more important object as feature size shrinks and cache capability increases more and more. Only process-level and circuit-level low power technologies can not meet our expectation for decreasing the leakage power in on-chip cache memory. Leakage power warrants architectural effort to take care of it.An overview of current architectural level low leakage power design and optimization techniques is made. By analyzing their advantages and disadvantages, the basic idea of cache leakage power optimization in architectural level is summarized. That is putting more cache lines into low leakage power mode without impacting processor performance. According to this basic idea, several aspects from different points of view are considered: distribution of leakage power, the access characteristics of different cache memory levels, optimizing the leakage power and the dynamic power at the same time, the balance of the power and performance. For on-chip cache memory in different memory levels and with different low power cache architecture, detailed researches have been done on the above issues. Several more effective cache leakage power optimization policies are proposed and estimated synthetically. The main contributions are as follows:1. An integrated evaluation system in architecture level for cache power optimization technology is proposed to show the efficiency of power reduction, performance protection and performance-power tradeoff. It can evaluate the cache power optimization technology which not only optimizes the cache leakage power but also optimizes the cache dynamic power. Besides evaluating the optimization effect for cache power, it can also evaluate the optimization effect for the whole microprocessor's power and the influence for microprocessor's performance.2. For on-chip drowsy instruction cache, firstly a multi-way way prediction policy using way predictor with two prediction ports is proposed, which is used in traditional front-end pipeline. This policy can optimize the leakage power and dynamic power in the instruction cache at the same time, reduce the performance penalty caused by incorrect way prediction, and balance the performance and power better. Secondly, phased cache architecture with on-demand wakeup policy is proposed, which is used in improved front-end pipeline. It can decrease the instruction cache leakage power and dynamic power more efficiently.3. For on-chip data cache with bit-line isolation technology, ELSS (Enhanced LRU-STRIDE-SEQ), a novel cache replacement policy is proposed. By redirecting sequential and stride data blocks fills to the same memory bank in data cache, the number of bank transition is reduced and the extra bank transition dynamic energy is saved. So the leakage power optimization effect of bit-line isolation technology for data cache is improved at last.4. For on-chip sleep data cache, SB_CLPE (Statistics-Based Cache Leakage Power Estimation) method is proposed and a software and hardware cooperating static self-adaptive cache decay policy is given. The mechanism of estimating the data cache leakage power by the cooperation of software and hardware during the pre-execution process of programs is designed to get the best decay interval which can acquire the lowest data cache leakage power for these programs. The best decay intervals for different programs and different phases of one program has been set after the pre-execution process, then the decay interval can be self-adaptive adjusted statically during the formal execution process of programs to acquire the lowest data cache leakage power and the better microprocessor's energy efficiency.5. For on-chip secondary cache, two leakage power optimization policies based on the on-chip cache hierarchies are proposed. One is C-SP&SD (Conserved State-Preserving & State-Destroying) policy; the other is S-SP&SD (Speculative State-Preserving & State-Destroying) policy. These two policies both combine the State-Preserving with the State-Destroying low leakage power mode. By keeping only one copy of a data block in cache hierarchies in active mode and turning others copies of this data block into the low power mode, more leakage power of on-chip secondary cache is decreased.Plenty of experiments are made. Results show that all the proposed architectural leakage power optimization mechanisms for different cache in cache hierarchies can achieve aggressive power saving without obvious performance reduction. The microprocessor's energy efficiency is also improved more effectively.