EPIP Micropcessor Parallel Instruction Cache Design

In computer architecture,processors’ access speed are much faster than mainmemory storage,this makes processors’ high-speed processing capability limited,andthe entire system is affected,so we need to design Cache in order to solve the problemof speed matching.The access speed of SRAM in cache is generally3~4times fasterthan main memory(DRAM).According to temporal locality and spatial locality,Cachecan greatly improve the processors’ efficiency.This major work is to design a multithreading non-blocking Cache used in the32-bit parallel microprocessor EPIP.The article first analyzes the need ofmultithreading non-blocking Cache,then put forward its timing requirements and oneimplementations,use SystemVerilog to model the program,and employ OVM libraryto setup the verification environment for establishment of performance evaluation.In order to achieve high performance design requirements to optimize thestructure of a variety of design.Use Cache buffer table and thread request order tablehardware structure to meet the multithreading and non-blocking requirements;In orderto improve Cache hit rate,set multi-way associative mode image;In the replacementstrategy,use LRU(Least Recently Used);In order to improve the virtual address tophysical address translation efficiency,add address search buffer structure.Validated more,the designed cache supports maximum8data request blocklength,and the shortest return period is5clock cycles,containing32KB dataSRAM.Use SMIC0.18um process synthesis,the maximum operating clock frequencyis250MHZ,and can meet the most multiple threads and advanced implementationprocessors’ demand.