Design And Impementation Of On-chip Cloud Architecture Flow Engine

Software research and development have witnessed a history with several phases, from the structured to the target-oriented, to the later component-oriented, and then to the service-oriented. On-chip cloud architecture is a kind of coarse-grain, loose-coupling and component-oriented application system framework, the development basis of which is programming. Owing to its merits of independence, loose coupling, reusability, scalability, and so on, on-chip cloud architecture has already attracted the massive attention of scholars both at home and aboard. And an in-depth research is of paramount significance for the development of applied system and electronic industry.In this study, service-oriented on-chip cloud, a new structure on FPGA is developed, in which a parallel processing of cloud computing is introduced into the design of integrated circuit. The basic process of the new structure is conducted by the following procedures:the concept of component in software field is adopted here; referring to that concept, the operation is atomized and the design is a course-grain instruction set; then, the function implementation module gets packaged as an atomic component for message delivery; afterwards, the atomic components between each other and those between the engine get connected through the write-only bus in the chip; besides, both the component calling and operating execution are controlled by the process engine which is core of the controlling system in the architecture. Through semantic process, it first receives the operation sequence of the needed components at the moment, and then packages the news for operation at unified node. The packaged news gets delivered to the node interface by the write-only bus and there the information interaction is finished. Data communication in on-chip cloud architecture is realized by the existence of write-only bus and its interconnection mechanism. The bus network topology is completed on the basis of Ethernet, as well as the designs of application layer, network layer and link layer. The three layers refer to access protocols of resource, unified structure element, and unified node interface. And through that node interface, components and engine get mounted to the write-only bus, which greatly reduces the interconnection between pins, simplifies the circuit design and improves parallel processing capability of cloud computing.In order to validate the architecture performance, an AVS encoder is designed and implemented in the research according to the integrated circuit of the on-chip cloud framework. First, the encoder’s functions are analyzed to fix its three module layers of demand, semantics and service. And three corresponding sets get deduced by their respective analyses. They are sets of atomic components, semantic process of AVS encoder and component forms of data frame together with the encoder atomic components. Once the semantic process is loaded to the process engine, the latter will automatically call the components in the encoder and implement that AVS encoder in the on-chip cloud architecture.In view of high capability of parallel processing on FPGA platform, AVS encoder atom component for image capture, transformation prediction atom component, encoding atom component and code stream concatenation atom component are designed and implemented with VHDL. In order to improve the encoder performance, manners like concurrent execution of atom components and parallel operation of process are adopted to realize real-time coding of high-resolution images. At last, on Xilinx XUP V5-LX110T FPGA platform, the real-time encoding of full I frame images of Dl resolution is achieved and then the encoded stream is delivered through Ethernet to the decoder and displayed by the player, well validating the reliability and instantaneity of the AVS encoder of on-chip cloud architecture.